计算机组成与设计：硬件/软件接口（英文版•第5版•亚洲版）

图书标准信息

• 作者 [美]David、John L.Hennessy 著
• 出版社 机械工业出版社
• 出版时间 2014-02
• 版次 5
• ISBN 9787111453161
• 定价 139.00元
• 装帧 平装
• 开本 16开
• 纸张 胶版纸
• 页数 704页
• 字数 100千字
• 正文语种 英语
• 原版书名 Computer Organization and Design：The Hardware/Software Interface, Fifth Edition, Asian Edition
• 丛书 经典原版书库

【内容简介】

《计算机组成与设计：硬件/软件接口(MPS版)(英文版·第5版·亚洲版》，本书内容： 这本最畅销的计算机组成与设计的经典教材经过全面修订，关注后PC时代发生在计算机体系结构领域的革命性变革（从单处理器发展到多核微处理器，从串行发展到并行），并强调了新出现的移动计算和云计算。为了研讨和强调这种重大的变化，本书更新了许多内容，重点介绍平板电脑、云体系结构以及ARM（移动计算设备）和x86（云计算）体系结构。

【作者简介】

　　JohnL.Hennessy，斯坦福大学校长，IEEE和ACM会士，美国国家工程研究院院士及美国科学艺术研究院院士。Hennessy教授因为在RISC技术方面做出了突出贡献而荣获2001年的Eckert-Mauchly奖章，他也是2001年SeymourCray计算机工程奖得主，并且和DavidA.Patterson分享了2000年JohnvonNeumann奖。DavidA．Patterson加州大学伯克利分校计算机科学系教授，美国国家工程院院士，美国国家科学院院士，IEEE和ACM会士。他因为教学成果显著而荣获了加州大学的杰出教学奖、ACM的Karlstrom奖、IEEE的Mulligan教育奖章和本科生教学奖。因为对RISC技术的贡献，他获得lEEE的技术成就奖和ACM的Eckert-Mauchly奖；而在RAID方面的贡献为他赢得了IEEEJohnson信息存储奖。他还和JohnL.Hennessy分享了IEEEJohnvonNeumann奖章和NECC&C奖金。Patterson还是美国艺术与科学院院士、美国计算机历史博物馆院士，并被选入硅谷工程名人堂。Patterson身为美国总统信息技术顾问委员会委员，还曾担任加州大学伯克利分校电子工程与计算机科学系计算机科学分部主任、计算机研究协会（CRA）主席和ACM主席。这一履历使他荣获了ACM和CRA颁发的杰出服务奖。

【目录】

Prefacev
AbouttheAuthorxiii
CHAPTERS
1ComputerAbstractionsandTechnology2
1.1Introduction3
1.2EightGreatIdeasinComputerArchitecture11
1.3BelowYourProgram13
1.4UndertheCovers16
1.5TechnologiesforBuildingProcessorsandMemory24
1.6Performance28
1.7ThePowerWall40
1.8TheSeaChange：TheSwitchfromUniprocessorstoMultiprocessors43
1.9RealStuff：BenchmarkingtheIntelCorei746
1.10FallaciesandPitfalls49
1.11ConcludingRemarks52
1.12HistoricalPerspectiveandFurtherReading54
1.13Exercises54

2Instructions：LanguageoftheComputer60
2.1Introduction62
2.2OperationsoftheComputerHardware63
2.3OperandsoftheComputerHardware66
2.4SignedandUnsignedNumbers73
2.5RepresentingInstructionsintheComputer80
2.6LogicalOperations87
2.7InstructionsforMakingDecisions90
2.8SupportingProceduresinComputerHardware96
2.9MIPSAddressingfor32-BitImmediatesandAddresses106
2.10ParallelismandInstructions：Synchronization116
2.11TranslatingandStartingaProgram118
2.12ACSortExampletoPutItAllTogether126
2.13AdvancedMaterial：CompilingC134
2.14RealStuff：ARMy7（32-bit）Instructions134
2.15RealStuff：x86Instructions138
2.16RealStuff：ARMv8（64-bit）Instructions147
2.17FallaciesandPitfalls148
2.18ConcludingRemarks150
2.19HistoricalPerspectiveandFurtherReading152
2.20Exercises153

3ArithmeticforComputers164
3.1Introduction166
3.2AdditionandSubtraction166
3.3Multiplication171
3.4Division177
3.5FloatingPoint184
3.6ParallelismandComputerArithmetic：SubwordParallelism210
3.7RealStuff：StreamingSIMDExtensionsandAdvancedVectorExtensionsinx86212
3.8GoingFaster：SubwordParallelismandMatrixMultiply213
3.9FallaciesandPitfalls217
3.10ConcludingRemarks220
3.11HistoricalPerspectiveandFurtherReading224
3.12Exercises225

4TheProcessor230
4.1Introduction232
4.2LogicDesignConventions236
4.3BuildingaDatapath239
4.4ASimpleImplementationScheme247
4.5AnOverviewofPipelining260
4.6PipelinedDatapathandControl274
4.7DataHazards：ForwardingversusStalling291
4.8ControlHazards304
4.9Exceptions313
4.10ParallelismviaInstructions320
4.11RealStuff：TheARMCortex-A8andIntelCorei7Pipelines332
4.12GoingFaster：Instruction-LevelParallelismandMatrixMultiply339
4.13AdvancedTopic：AnIntroductiontoDigitalDesignUsingaHardware
DesignLanguagetoDescribeandModelaPipelineandMorePipelining
Illustrations342
4.14FallaciesandPitfalls343
4.15CondudingRemarks344
4.16HistoricalPerspectiveandFurtherReading345
4.17Exercises345

5LargeandFast：ExploitingMemoryHierarchy360
5.1Introduction362
5.2MemoryTechnologies366
5.3TheBasicsofCaches371
5.4MeasuringandImprovingCachePerformance386
5.5DependableMemoryHierarchy406
5.6VirtualMachines412
5.7VirtualMemory415
5.8ACommonFrameworkforMemoryHierarchy442
5.9UsingaFinite-StateMachinetoControlaSimpleCache449
5.10ParallelismandMemoryHierarchies：CacheCoherence454
5.11ParallelismandMemoryHierarchy：RedundantArraysofInexpensiveDisks458
5.12AdvancedMaterial：ImplementingCacheControllers458
5.13RealStuff：TheARMCortex-A8andIntelCorei7MemoryHierarchies459
5.14GoingFaster：CacheBlockingandMatrixMultiply463
5.15FallaciesandPitfalls466
5.16GoncludingRemarks470
5.17HistoricalPerspectiveandFurtherReading471
5.18Exercises471

6ParallelProcessorsfromClienttoCloud488
6.1Introduction490
6.2TheDifficultyofCreatingParallelProcessingPrograms492
6.3SISD，MIMD，SIMD，SPMD，andVector497
6.4HardwareMultithreading504
6.5MulticoreandOtherSharedMemoryMultiprocessors507
6.6IntroductiontoGraphicsProcessingUnits512
6.7Clusters，WarehouseScaleComputers，andOtherMessage-PassingMultiprocessors519
6.8IntroductiontoMultiprocessorNetworkTopologies524
6.9CommunicatingtotheOutsideWorld：ClusterNetworking527
6.10MultiprocessorBenchmarksandPerformanceModels528
6.11RealStuff：BenchmarkingIntelCorei7versusNVIDIATeslaGPU538
6.12GoingFaster：MultipleProcessorsandMatrixMultiply543
6.13FallaciesandPitfalls546
6.14ConcludingRemarks548
6.15HistoricalPerspectiveandFurtherReading551
6.16Exercises551

APPENDICES
AAssemblers，Linkers，andtheSPiMSimulatorA-2
A.1IntroductionA-3
A.2AssemblersA-IO
A.3LinkersA-18
A.4LoadingA-19
A.5MemoryUsageA-20
A.6ProcedureCallConventionA-22
A.7ExceptionsandInterruptsA-33
A.8InputandOutputA-38
A.9SPIMA-40
A.10MIPSR2000AssemblyLanguageA-45
A.11ConcludingRemarksA-81
A.12ExercisesA-82

BTH-2HighPerformanceComputingSystemB-2
B.1IntroductionB-3
B.2ComputeNodeB-3
B.3TheFrontendProcessorsB-5
B.4TheInterconnectB-6
B.5TheSoftwareStackB-7
B.6LINPACKBenchmarkRun（HPL）B-7
B.7ConcludingRemarksB-8

FNetworks-on-ChipF-2
F.1IntroductionF-3
F.2CommunicationCentricDesignF-3
F.3TheDesignSpaceExplorationofNoCsF-5
F.4RouterMicro-architectureF-8
F.5PerformanceMetricF-9
F.6ConcludingRemarksF-9
IndexI-1