专业集成电路

图书标准信息

• 作者 内库加（Farzad Nekoogar） 著
• 出版社 清华大学出版社
• 出版时间 2009-11
• 版次 1
• ISBN 9787302213420
• 定价 25.00元
• 装帧 平装
• 开本 16开
• 纸张 胶版纸
• 页数 189页
• 正文语种 简体中文，英语

【内容简介】

　　《专用集成电路时序验证》是近10年来惟一一本专门讨论时序及时序验证的专著，共分4章。《专用集成电路时序验证》全面讨论了静态时序验证的各方面内容；全书不仅紧密结合电路图和波形图进行讲解，还结合Synopsys公司的逻辑综合和静态时序分析工具讲解如何通过命令加以实现；介绍过程中不仅从理论上阐述了延迟模型，而且注重实践环节，引入了大量实际示例加以深入探讨。这种写作风格将促进读者能够更全面、细致地理解所讲内容，因此《专用集成电路时序验证》十分适合自学。

【作者简介】

　　内库加（FarzadNekoogar）isDirectorofDesignServicesatSiliconDesignsInternational.Farzadhasextensivepracticalexpe-rienceverifyingtimingofASICs，FPGAs，andsystems-on-a-chip.HeistheauthorofDigitalControlUsingDigitalSig-nalProcessing，publishedbyPrenticeHallPTR.Hehaslec-turedattheUniversityofCaliforniaatBerkeleyonsignalprocessing，controlsystems，andtheoreticalphysics（specifi-cally，SuperstringTheory）.HeiscurrentlyalecturerattheDepartmentofAppliedScienceattheUniversityofCalifor-niaatDavis.
　　Farzad，seenhereinDecember1992atStanfordUniversity，withSirRogerPenrose.Farzadwrites："Inthisbookwetrytosolvetimingissuesrelatedtodesignofmicro-chips.IamhonoredtobepicturedherewithSirRogerPenrose，oneofthemostbril-liantscientistsofalltime，whohasauthoredsomeofthemostcomplextheoriesaboutspace-time，contributingalottoourunderstandingoftheuniverse."

【目录】

ListofFigures
ListofTables
Preface
Acknowledgments
1IntroductiontoTimingVerification
1.1Introduction
1.2OverviewofTimingVerification
1.2.1Intrinsicvs.ExtrinsicDelay
1.2.2PathDelay
1.3InterfaceTimingAnalysis

2ElementsofTimingVerification
2.1Introduction
2.2ClockDefinitions
2.2.1GatedClocks
2.2.2ClockSkewsandMultipleClockGroups
2.2.3MultifrequencyClocks
2.2.4MultiphaseClocks
2.3MoreonSTA
2.3.1FalsePaths
2.3.2MulticyclePathAnalysis
2.3.3TimingSpecifications
2.3.4TimingChecks
2.4TimingAnalysisofPhase-LockedLoops
2.4.1PLLBasics
2.4.2PLLIdealBehavior
2.4.3PLLErrors

3TiminginASICs
3.1Introduction
3.2PrelayoutTiming
3.2.1RTLvs.Gate-LevelTiming
3.2.2TiminginRTLCode
3.2.3DelaywithaContinuousAssignmentStatement
3.2.4DelayinaProcessStatement
3.2.6Intra-AssignmentDelays
3.2.6TheVerilogSpecifyBlock
3.2.7Timingin-GateLevelCode
3.2.8SynthesisandTimingConstraints
3.2.9DesignRuleConstraints
3.2.10OptimizationConstrAints
3.2.11GateandWire-LoadModels
3.2.12TheSynthesisFlow
3.2.13SynthesisTips
3.2.14BackAnnotationtoGate-LevelRTL
3.3Post.layoutTiming
3.3.1Man-A1Line-PropagationDelayCalculations
3.3.2Signal-LineCapacitanceCalculation
3.3.3SignalLineResistanceCalculation
3.3.4SignalTraceRCDelayEvaluation
3.4ASICSign-OffChecklist
3.4.1LibraryDevelopment
3.4.2FunctionalSpecification
3.4.3RTLCoding
3.4.4SimulationsofRTL
3.4.5LogicSynthesis
3.4.6TestInsertionandATPG
3.4.7PostsynthesisGate-LevelSimulationorStaticTimingAnalysis
3.4.8Floorplsnning
3.4.9PlaceandRoute
3.4.10FinalVerificationoftheExtractedNetlist
3.4.11MaskGenerationandFabrication
3.4.12Testing

4ProgrAmmableLogicBasedDesign
4.1Introduction
4.2ProgrammableLogicStructures
4.2.1LogicBlock
4.2.2Input/OutputBlock
4.2.3RoutingFacilities
4.3DesignFlow
4.4TimingParameters
4.4.1TimingDeratingFactors
4.4.2GradingProgrammableLogicDevicesbySpeed
4.4.3Beet-CaseDelayValues
4.5TimingAnalysis
4.5.1ActelACTFPGAFsmily
4.5.2ActelACT3Architecture
4.5.3ActelACT3TimingModel
4.5.4AlteraFLEX8000
4.5.5AlteraFLEX8000Architecture
4.5.6AlteraFLEX8000TimingModel
4.5.7XilinxXC3000/XC4000FPGAFamilies
4.5.8XilinxXC9500CPLD
4.5.9XilinxXC9500CPLDArchitecture
4.5.10XilinxXC9500CPLDTimingModel
4.6HDLSynthesis
4.7SoftwareDevelopmentSystems
4.7.1TimingConstraints
4.7.2OperatingConditions
4.7.3StaticTimingAnalysis
4.7.4Vendor-SpecificTiming-VerificationTools
4.7.5ActelDesigner
4.7.6AlteraMAX+PLUSII
4.7.7XilinxXACT/M1
APrimeTime
BPearl
CTimingDesigner
DTransistor-LevelTimingVerification
References
Index
AbouttheAuthor