系统集成：从晶体管设计到大规模集成电路（影印版）

图书标准信息

• 作者 [德]霍夫曼 著
• 出版社 科学出版社
• 出版时间 2007-01
• 版次 1
• ISBN 9787030182555
• 定价 66.00元
• 装帧 平装
• 开本 16开
• 纸张 胶版纸
• 页数 490页
• 字数 803千字
• 正文语种 英语
• 丛书 国外电子信息精品著作

【内容简介】

　　本书介绍了涉及集成电路组件的集成和设计的较宽范围的内容，提供给读者用简单公式估计晶体管几何尺寸和推演电路行为的方法。这本独特的书广泛覆盖场效应管的设计、MOS管的建模和数字CMOS集成电路设基础以及MOS存储器结构和设计。本书突出了在片上系统设计和集成方面知识增加的需求，第一次在单本中覆盖半导体物理学、数字VLSI设计和模拟集成电路，介绍了集成电路半导体组件的基本行为和基于MOS与BiCMOS工艺的数字和模拟集成电路的设计。

【目录】

Preface
Acknowledgments
PhysicalConstantsandConversionFactors
Symbols
1SemiconductorPhysics
1.1BandTheoryofSolids
1.2DopedSemiconductor
1.3SemiconductorinEquilibrium
1.3.1Fermi-DiracDistributionFunction
1.3.2CarrierConcentrationatEquilibrium
1.3.3DensityProductatEquilibrium
1.3.4RelationshipbetweenEnergy,Voltage,andElectricalField
1.4ChargeTransport
1.4.1DriftVelocity
1.4.2DriftCurrent
1.4.3DiffusionCurrent
1.4.4ContinuityEquation
1.5Non-EquilibriumConditions
Problems
References
FurtherReading
2pn-Junction
2.1InhomogeneouslyDopedn-typeSemiconductor
2.2pn-JunctionatEquilibrium
2.3Biasedpn-Junction
2.3.1DensityProductunderNon-EquilibriumConditions
2.3.2Current-VoltageRelationship
2.3.3DeviationfromtheCurrent-VoltageRelationship
2.3.4VoltageReferencePoint
2.4CapacitanceCharacteristic
2.4.1DepletionCapacitance
2.4.2DiffusionCapacitance
2.5SwitchingCharacteristic
2.6JunctionBreakdown
2.7Modelingthepn-Junction
2.7.1DiodeModelforCADApplications
2.7.2DiodeModelforStaticCalculations
2.7.3DiodeModelforSmall-SignalCalculations
Problems
References
3BipolarTransistor
3.1BipolarTechnologies
3.2TransistorOperation
3.2.1Current-VoltageRelationship
3.2.2TransistorunderReverseBiasedCondition
3.2.3VoltageSaturation
3.2.4TemperatureBehavior
3.2.5BreakdownBehavior
3.3Second-OrderEffects
3.3.1HighCurrentEffects
3.3.2Base-WidthModulation
3.3.3CurrentCrowding
3.4AlternativeTransistorStructures
3.5ModelingtheBipolarTransistor
3.5.1TransistorModelforCADApplications
3.5.2TransistorModelforStaticCalculations
3.5.3TransistorModelforSmall-SignalCalculations
3.5.4TransitTimeDetermination
Problems
References
FurtherReading
4MOSTransistor
4.1CMOSTechnology
4.2TheMOSStructure
4.2.1CharacteristicoftheMOSStructure
4.2.2CapacitanceBehavioroftheMOSStructure
4.2.3Flat-BandVoltage
4.3EquationsoftheMOSStructure
　4.3.1ChargeEquationsoftheMOSStructure
4.3.2SurfaceVoltageatStrongInversion
4.3.3ThresholdVoltageandBodyEffect
4.4MOSTransistor
4.4.1Current-VoltageCharacteristicatStrongInversion
4.4.2ImprovedTransistorEquation
4.4.3Current-VoltageCharacteristicatWeakInversion
4.4.4TemperatureBehavior
4.5Second-OrderEffects
4.5.1MobilityDegradation
4.5.2ChannelLengthModulation
4.5.3ShortChannelEffects
4.5.4HotElectrons
4.5.5Gate-InducedDrainLeakage
4.5.6BreakdownBehavior
4.5.7Latch-upEffect
4.6PowerDevices
4.7ModelingoftheMOSTransistor
4.7.1TransistorModelforCADApplications
4.7.2TransistorModelforStaticandDynamicCalculations
4.7.3TransistorModelforSmall-SignalCalculations
Problems
AppendixACurrent-VoltageEquationoftheMOSTransistor　underWeakInversionCondition
References
FurtherReading
5BasicDigitalCMOSCircuits
5.1GeometricDesignRules
5.2ElectricalDesignRules
5.3MOSInverter
5.3.1DepletionLoadInverter
5.3.2EnhancementLoadInverter
5.3.3PMOSLoadInverter
5.3.4CMOSInverter
5.3.5RatioedDesignIssues
5.4SwitchingPerformanceoftheInverters
5.5BufferStages
5.5.1SuperBuffer
5.5.2BootstrapBuffer
5.6Input/OutputStage
5.6.1InputStage
5.6.2OutputStage
5.6.3ESDProtection
Problems
References
6CombinationalandSequentialCMOSCircuits
6.1StaticCombinationalCircuits
6.1.1ComplementaryCircuits
6.1.2PMOSLoadCircuits
6.1.3Pass-TransistorCircuits
6.2ClockedCombinationalCircuits
6.2.1ClockedCMOSCircuits(C2MOS)
6.2.2DominoCircuits
6.2.3NORACircuits
6.2.4DifferentialCascadedVoltageSwitchCircuits(DCVS)
6.2.5SwitchingPerformanceofRatiolessLogic
6.3HighSpeedCircuits
6.4LogicArrays
6.4.1Decoder
6.4.2ProgrammableLogicArray
6.5SequentialCircuits
6.5.1Flip-flop
6.5.2Two-PhaseClockedRegister
6.5.3One-PhaseClockedRegister
6.5.4ClockDistributionandGeneration
Problems
References
FurtherReading
7MOSMemories
7.1ReadOnlyMemory
7.2ElectricallyProgrammableandOpticallyErasableMemory
7.2.1EPROMMemoryArchitecture
7.2.2CurrentSenseAmplifier
7.3ElectricallyErasableandProgrammableReadOnlyMemories
7.3.1EEPROMMemoryCells
7.3.2FlashMemoryArchitectures
7.3.3On-ChipVoltageGenerators
7.4StaticMemories
7.4.1StaticMemoryCells
7.4.2SRAMMemoryArchitecture
7.4.3AddressTransitionDetection
7.5DynamicMemories
7.5.1One-TransistorCell
7.5.2BasicDRAMMemoryCircuits
7.5.3DRAMArchitecture
7.5.4RadiationEffectsinMemories
Problems
References
FurtherReading
8BasicAnalogCMOSCircuits
8.1CurrentMirror
8.1.1ImprovedCurrentSources
8.2SourceFollower
8.3BasicAmplifierPerformance
8.3.1MillerEffect
8.3.2DifferentialStagewithSymmetricalOutput
8.3.3DifferentialInputStagewithSingle-EndedOutput
Problems
AppendixATransferFunctions
FurtherReading
9CMOSAmplifiers
9.1MillerAmplifier
9.2FoldedCascodeAmplifier
9.3FoldedCascodeAmplifierwithImprovedDrivingCapability
Problems
References
10BICMOS
10.1CurrentSteeringTechniques
10.1.1CMLCircuits
10.1.2ECLCircuits
10.2BICMOSBufferandGates
10.3Band-GapReferenceCircuits
10.4AnalogApplications
10.4.1OffsetVoltageofBipolarandMOSTransistors
10.4.2ComparisonofSmall-SignalPerformance
Problems
References
Index