计算机组成与设计：硬件/软件接口（英文版·第4版·ARM版）

图书标准信息

• 作者 [美]帕特林 著
• 出版社 机械工业出版社
• 出版时间 2010-04
• 版次 1
• ISBN 9787111302889
• 定价 95.00元
• 装帧 平装
• 开本 16开
• 纸张 胶版纸
• 页数 689页
• 正文语种 英语
• 丛书 经典原版书库

【内容简介】

《计算机组成与设计：硬件/软件接口（英文版·第4版·ARM版）》采用了一个MIPS处理器来展示计算机硬件技术、流水线、存储器层次结构以及I／O等基本功能。此外。《计算机组成与设计：硬件/软件接口（英文版·第4版·ARM版）》还包括一些关于x86架构的介绍。

这本最畅销的计算机组成书籍经过全面更新，关注现今发生在计算机体系结构领域的革命性变革：从单处理器发展到多核微处理器。此外，出版这本书的ARM版是为了强调嵌入式系统对于全亚洲计算行业的重要性，并采用ARM处理器来讨论实际计算机的指令集和算术运算。因为ARM是用于嵌入式设备的最流行的指令集架构，而全世界每年约销售40亿个嵌入式设备。与前几版一样。

采用ARMv6（ARM11系列）为主要架构来展示指令系统和计算机算术运算的基本功能。

覆盖从串行计算到并行计算的革命性变革，新增了关于并行化的一章，并且每章中还有一些强调并行硬件和软件主题的小节。

新增一个由NVIDIA的首席科学家和架构主管撰写的附录，介绍了现代GPU的出现和重要性，首次详细描述了这个针对可视计算进行了优化的高度并行化、多线程、多核的处理器。

描述一种度量多核性能的独特方法——“Rooflinemodel”，自带benchmark测试和分析AMDOpteronX4、IntelXeo5000、SunUltraSPARCT2和IBMCell的性能。

涵盖了一些关于闪存和虚拟机的新内容。提供了大量富有启发性的练习题，内容达200多页。

将AMDOpteronX4和IntelNehalem作为贯穿《计算机组成与设计：硬件/软件接口（英文版·第4版·ARM版）》的实例。

用SPECCPU2006组件更新了所有处理器性能实例。

【作者简介】

DavidA.Patterson，加州大学伯克利分校计算机科学系教授。美国国家工程研究院院士。IEEE和ACM会士。曾因成功的启发式教育方法被IEEE授予JamesH.Mulligan，Jr教育奖章。他因为对RISC技术的贡献而荣获1995年IEEE技术成就奖，而在RAID技术方面的成就为他赢得了1999年IEEEReynoldJohnson信息存储奖。2000年他~13JohnL.Hennessy分享了JohnvonNeumann奖。

JohnL.Hennessy，斯坦福大学校长，IEEE和ACM会士。美国国家工程研究院院士及美国科学艺术研究院院士。Hennessy教授因为在RISC技术方面做出了突出贡献而荣获2001年的Eckert-Mauchly奖章.他也是2001年SeymourCray计算机工程奖得主。并且和DavidA.Patterson分享了2000年JohnvonNeumann奖。

【目录】

Contents

Prefacexv

CHAPTERS

ComputerAbstractionsandTechnology2

1.1Introduction3

1.2BelowYourProgram10

1.3UndertheCovers13

1.4Performance26

1.5ThePowerWall39

1.6TheSeaChange:TheSwitchfromUniprocessorstoMultiprocessors41

1.7RealStuff:ManufacturingandBenchmarkingtheAMDOpteronX444

1.8FallaciesandPitfalls51

1.9ConcludingRemarks54

1.10HistoricalPerspectiveandFurtherReading55

1.11Exercises56

Instructions:LanguageoftheComputer74

2.1Introduction76

2.2OperationsoftheComputerHardware77

2.3OperandsoftheComputerHardware80

2.4SignedandUnsignedNumbers86

2.5RepresentingInstructionsintheComputer93

2.6LogicalOperations100

2.7InstructionsforMakingDecisions104

2.8SupportingProceduresinComputerHardware113

2.9CommunicatingwithPeople122

2.10ARMAddressingfor32-BitImmediatesandMoreComplexAddressingModes127

2.11ParallelismandInstructions:Synchronization133

2.12TranslatingandStartingaProgram135

2.13ACSortExampletoPutItAllTogether143

:Thisiconidenti.esmaterialontheCD

2.14ArraysversusPointers152

2.15AdvancedMaterial:CompilingCandInterpretingJava156

2.16RealStuff:MIPSInstructions156

2.17RealStuff:x86Instructions161

2.18FallaciesandPitfalls170

2.19ConcludingRemarks171

2.20HistoricalPerspectiveandFurtherReading174

2.21Exercises174

ArithmeticforComputers214

3.1Introduction216

3.2AdditionandSubtraction216

3.3Multiplication220

3.4Division226

3.5FloatingPoint232

3.6ParallelismandComputerArithmetic:Associativity258

3.7RealStuff:FloatingPointinthex86259

3.8FallaciesandPitfalls262

3.9ConcludingRemarks265

3.10HistoricalPerspectiveandFurtherReading268

3.11Exercises269

TheProcessor284

4.1Introduction286

4.2LogicDesignConventions289

4.3BuildingaDatapath293

4.4ASimpleImplementationScheme302

4.5AnOverviewofPipelining316

4.6PipelinedDatapathandControl330

4.7DataHazards:ForwardingversusStalling349

4.8ControlHazards361

4.9Exceptions370

4.10ParallelismandAdvancedInstruction-LevelParallelism377

4.11RealStuff:theAMDOpteronX4(Barcelona)Pipeline390

4.12AdvancedTopic:anIntroductiontoDigitalDesignUsingaHardwareDesignLanguagetoDescribeandModelaPipelineandMorePipeliningIllustrations392

4.13FallaciesandPitfalls393

4.14ConcludingRemarks394

4.15HistoricalPerspectiveandFurtherReading395

4.16Exercises395

LargeandFast:ExploitingMemoryHierarchy436

5.1Introduction438

5.2TheBasicsofCaches443

5.3MeasuringandImprovingCachePerformance461

5.4VirtualMemory478

5.5ACommonFrameworkforMemoryHierarchies504

5.6VirtualMachines511

5.7UsingaFinite-StateMachinetoControlaSimpleCache515

5.8ParallelismandMemoryHierarchies:CacheCoherence520

5.9AdvancedMaterial:ImplementingCacheControllers524

5.10RealStuff:theAMDOpteronX4(Barcelona)andIntelNehalemMemoryHierarchies525

5.11FallaciesandPitfalls529

5.12ConcludingRemarks533

5.13HistoricalPerspectiveandFurtherReading534

5.14Exercises534

StorageandOtherI/OTopics554

6.1Introduction556

6.2Dependability,Reliability,andAvailability559

6.3DiskStorage561

6.4FlashStorage566

6.5ConnectingProcessors,Memory,andI/ODevices568

6.6InterfacingI/ODevicestotheProcessor,Memory,andOperatingSystem572

6.7I/OPerformanceMeasures:ExamplesfromDiskandFileSystems582

6.8DesigninganI/OSystem584

6.9ParallelismandI/O:RedundantArraysofInexpensiveDisks585

6.10RealStuff:SunFirex4150Server592

6.11AdvancedTopics:Networks598

6.12FallaciesandPitfalls599

6.13ConcludingRemarks603

6.14HistoricalPerspectiveandFurtherReading604

6.15Exercises605

Multicores,Multiprocessors,andClusters616

7.1Introduction618

7.2TheDif.cultyofCreatingParallelProcessingPrograms620

7.3SharedMemoryMultiprocessors624

7.4ClustersandOtherMessage-PassingMultiprocessors627

7.5HardwareMultithreading631

7.6SISD,MIMD,SIMD,SPMD,andVector634

7.7IntroductiontoGraphicsProcessingUnits640

7.8IntroductiontoMultiprocessorNetworkTopologies646

7.9MultiprocessorBenchmarks650

7.10Roo.ine:ASimplePerformanceModel653

7.11RealStuff:BenchmarkingFourMulticoresUsingtheRoo.ineModel661

7.12FallaciesandPitfalls670

7.13ConcludingRemarks672

7.14HistoricalPerspectiveandFurtherReading674

7.15Exercises674IndexI-1

CD-ROMCONTENT

GraphicsandComputingGPUsA-2

A.1IntroductionA-3

A.2GPUSystemArchitecturesA-7

A.3ScalableParallelism–ProgrammingGPUsA-12

A.4MultithreadedMultiprocessorArchitectureA-25

A.5ParallelMemorySystemG.6FloatingPointA-36

A.6FloatingPointArithmeticA-41

A.7RealStuff:TheNVIDIAGeForce8800A-46

A.8RealStuff:MappingApplicationstoGPUsA-55

A.9FallaciesandPitfallsA-72

A.10ConcludingRemarksA-76

A.11HistoricalPerspectiveandFurtherReadingA-77

ARMandThumbAssemblerInstructionsB1-2

B1.1UsingThisAppendixB1-3B1.2SyntaxB1-4B1.3AlphabeticalListofARMandThumbInstructionsB1-8B1.4ARMAssemblerQuickReferenceB1-49B1.5GNUAssemblerQuickReferenceB1-60

ARMandThumbInstructionEncodingsB2-2

B2.1ARMInstructionSetEncodingsB2-3

B2.2ThumbInstructionSetEncodingsB2-9

B2.3ProgramStatusRegistersB2-11

InstructionCycleTimingsB3-2

B3.1UsingtheInstructionSetCycleTimingTablesB3-3B3.2ARM7TDMIInstructionCycleTimingsB3-5B3.3ARM9TDMIInstructionCycleTimingsB3-6B3.4StrongARM1InstructionCycleTimingsB3-8B3.5ARM9EInstructionCycleTimingsB3-9B3.6ARM10EInstructionCycleTimingsB3-11B3.7IntelXScaleInstructionCycleTimingsB3-12B3.8ARM11CycleTimingsB3-14

CTheBasicsofLogicDesignC-2

C.1IntroductionC-3

C.2Gates,TruthTables,andLogicEquationsC-4

C.3CombinationalLogicC-9

C.4UsingaHardwareDescriptionLanguageC-20

C.5ConstructingaBasicArithmeticLogicUnitC-26

C.6FasterAddition:CarryLookaheadC-38

C.7ClocksC-48

C.8MemoryElements:Flip-Flops,Latches,andRegistersC-50

C.9MemoryElements:SRAMsandDRAMsC-58

C.10Finite-StateMachinesC-67

C.11TimingMethodologiesC-72

C.12FieldProgrammableDevicesC-78

C.13ConcludingRemarksC-79

C.14ExercisesC-80

DMappingControltoHardwareD-2

D.1IntroductionD-3

D.2ImplementingCombinationalControlUnitsD-4

D.3ImplementingFinite-StateMachineControlD-8

D.4ImplementingtheNext-StateFunctionwithaSequencerD-22

D.5TranslatingaMicroprogramtoHardwareD-28

D.6ConcludingRemarksD-32

D.7ExercisesD-33

ADVANCEDCONTENT

Section2.15CompilingCandInterpretingJavaSection4.12AnIntroductiontoDigitalDesignUsingaHardwareDesignLanguagetoDescribeandModelaPipelineandMorePipeliningIllustrationsSection5.9ImplementingCacheControllersSection6.11Networks

HISTORICALPERSPECTIVES&FURTHERREADING

Chapter1ComputerAbstractionsandTechnology:Section1.10Chapter2Instructions:LanguageoftheComputer:Section2.20Chapter3ArithmeticforComputers:Section3.10Chapter4TheProcessor:Section4.15Chapter5LargeandFast:ExploitingMemoryHierarchy:Section5.13Chapter6StorageandOtherI/OTopics:Section6.14Chapter7Multicores,Multiprocessors,andClusters:Section7.14AppendixAGraphicsandComputingGPUs:SectionA.11

TUTORIALS

VHDL

Verilog

SOFTWARE

XilinxFPGADesign,SimulationandSynthesisSoftwareQEMUhttp://www.nongnu.org/qemu/about.html

GlossaryG-1IndexI-1FurtherReadingFR-1