数字集成电路设计:从VLSI体系结构到CMOS制造
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江苏南京
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作者(瑞士)Kaeslin
出版社人民邮电出版社
ISBN9787115223586
出版时间2010-05
版次1
装帧平装
开本16开
纸张胶版纸
页数845页
字数99999千字
定价119元
上书时间2024-06-03
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基本信息
书名:数字集成电路设计:从VLSI体系结构到CMOS制造
定价：119.00元
作者:(瑞士)Kaeslin
出版社：人民邮电出版社
出版日期：2010-05-01
ISBN：9787115223586
字数：872000
页码：845
版次：1
装帧：平装
开本：12开
商品重量：
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内容提要
本书从架构与算法讲起，介绍了功能验证、VHDL建模、同步电路设计、异步数据获取、能耗与散热、信号完整性、物理设计、设计验证等技术，还讲解了VLSI经济运作与项目管理，并简单阐释了CMOS技术的基础知识，全面覆盖了数字集成电路的整个设计开发过程。 本书既可作为高等院校微电子、电子技术等相关专业高年级师生和研究生的参考教材，也可供半导体行业工程师参考。
目录
Chapter 1 Introduction to Microelectronics 1.1 Economic impact 1.2 Concepts and terminology 1.2.1 The Guinnesook of records point of view 1.2.2 The marketing point of view 1.2.3 The fabrication point of view 1.2.4 The design engineer's point of view 1.2.5 The business point of view 1.3 Design flow in digital VLSI 1.3.1 The Y-chart, a map of digital electronic systems 1.3.2 Major stages in VLSI design 1.3.3 Cell libraries 1.3.4 Electronic design automation software 1.4 Field-programmable logic 1.4.1 Configuration technologies 1.4.2 Organization of hardware resources 1.4.3 Commercial products 1.5 Problems 1.6 Appendix I: A brief glossary of logic families 1.7 Appendix II: An illustrated glossary of circuit-related terms Chapter 2 From Algorithms to Architectures 2.1 The goals of architecture design 2.1.1 Agenda 2.2 The architectural antipodes 2.2.1 What makes an algorithm suitable for a dedicated VLSI architecture? 2.2.2 There is plenty of land between the architectural antipodes 2.2.3 Assemblies of general-purpose and dedicated processing units 2.2.4 Coprocessors 2.2.5 Application-specific instruction set processors 2.2.6 Configurable computing 2.2.7 Extendable instruction set processors 2.2.8 Digest 2.3 A transform approach to VLSI architecture design 2.3.1 There is room for remodelling in the algorithmic domain 62 2.3.2 ...and there is room in the architectural domain 2.3.3 Systems engineers and VLSI designers must collaborate 2.3.4 A graph-based formalism for describing processing algorithms 2.3.5 The isomorphic architecture 2.3.6 Relative merits of architectural alternatives 2.3.7 Computation cycle versus clock period 2.4 Equivalence transforms for combinational computations 2.4.1 Common assumptions 2.4.2 Iterative decomposition 2.4.3 Pipelining 2.4.4 Replication 2.4.5 Time sharing 2.4.6 Associativity transform 2.4.7 Other algebraic transforms 2.4.8 Digest 2.5 Options for temporary storage of data 2.5.1 Data access patterns 2.5.2 Available memory configurations and area occupation 2.5.3 Storage capacities 2.5.4 Wiring and the costs of going off-chip 2.5.5 Latency and timing 2.5.6 Digest 2.6 Equivalence transforms for nonrecursive computations 2.6.1 Retiming 2.6.2 Pipelining revisited 2.6.3 Systolic conversion 2.6.4 Iterative decomposition and time-sharing revisited 2.6.5 Replication revisited 2.6.6 Digest 2.7 Equivalence transforms for recursive computations 2.7.1 The feedback bottleneck 2.7.2 Unfolding of first-order loops 2.7.3 Higher-order loops 2.7.4 Time-variant loops 2.7.5 Nonlinear or general loops 2.7.6 Pipeline interleaving is not an equivalence transform 2.7.7 Digest 2.8 Generalizations of the transform approach 2.8.1 Generalization to other levels of detail 2.8.2 Bit-serial architectures 2.8.3 Distributed arithmetic 2.8.4 Generalization to other algebraic structures 2.8.5 Digest 2.9 Conclusions 2.9.1 Summary 2.9.2 The grand architectural alternatives from an energy point of view 2.9.3 A guide to evaluating architectural alternatives 2.10 Problems 2.11 Appendix I: A brief glossary of algebraic structures 2.12 Appendix II: Area and delay figures of VLSI subfunctions Chapter 3 Functional Verification Chapter 4 Modelling Hardware with VHDL Chapter 5 The Case for Synchronous Design Chapter 6 Clocking of Synchronous Circuits Chapter 7 Acquisition of Asynchronous Data Chapter 8 Gate- and Transistor-Level Design Chapter 9 Energy Efficiency and Heat Removal Chapter 10 Signal Integrity Chapter 11 Physical Design Chapter 12 Design Verification Chapter 13 VLSI Economics and Project Management Chapter 14 A Primer on CMOS Technology Chapter 15 Outlook Appendix A Elementary Digital Electronics Appendix B Finite State Machines Appendix C VLSI Designer’s Checklist Appendix D Symbols and constants References Index
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