计算机组成与设计：硬件/软件接口RISC-V版（英文版·原书第2版）9787111742661
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作者[美]戴维·A. 帕特森(David A. Patterson) [美]约翰·L. 亨尼斯(John L. Hennessy)
出版社机械工业
ISBN9787111742661
出版时间2024-01
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定价199元
货号31968169
上书时间2024-12-18
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作者简介
戴维·A.帕特森（DavidA.Patterson）<br/>自1977年加入加州大学伯克利分校以来，他一直在该校教授计算机体系结构课程，并在那里担任计算机科学Pardee教席。他曾因教学工作获得加州大学杰出教学奖、ACMKarlstrom奖、IEEEMulligan教育奖章以及IEEE本科教学奖。因为对RISC的贡献，Patterson获得了IEEE技术进步奖和ACMEckert-Mauchly奖，并因为对RAID的贡献分享了IEEEJohnson信息存储奖。他和Hennessy共同获得了IEEEJohnvonNeumann奖章以及C&C奖金。与Hennessy一样，Patterson是美国国家工程院、美国国家科学院、美国艺术与科学院和计算机历史博物馆院士，ACM和IEEE会士，并入选了硅谷工程名人堂。他曾担任加州大学伯克利分校电气工程与计算机科学（EECS）系计算机科学分部主任、计算研究学会主席和ACM主席。这些工作使他获得了ACM、CRA以及SIGARCH的杰出服务奖。他因在科学普及和计算多样化方面的贡献而获得了Tapia成就奖，并与Hennessy共同获得了2017年ACM图灵奖。<br/>在伯克利，Patterson领导了RISCI的设计与实现工作，这可能是第一台VLSI精简指令系统计算机，为商用SPARC体系结构奠定了基础。他也是廉价磁盘冗余阵列（RAID）项目的领导者，RAID技术引导许多公司开发出了高可靠的存储系统。他还参加了工作站网络（NOW）项目，正是因为该项目，才有了被互联网公司广泛使用的集群技术以及后来的云计算。这些项目获得了四个ACM最佳论文奖。2016年，他成为伯克利的荣休教授和谷歌杰出工程师，在谷歌，他致力于面向机器学习的领域定制体系结构的研究工作。他还是RISC-V国际协会副主席和RISC-V国际开源实验室主任。<br/>约翰·L.亨尼斯（JohnL.Hennessy）<br/>斯坦福大学第十任校长，从1977年开始任教于该校电气工程与计算机科学系。Hennessy是IEEE和ACM会士，美国国家工程院、美国国家科学院、美国哲学院以及美国艺术与科学院院士。Hennessy获得的众多奖项包括：2001年ACMEckert-Mauchly奖（因对RISC的贡献），2001年SeymourCray计算机工程奖，2000年与Patterson共同获得IEEEJohnvonNeumann奖章，2017年又与Patterson共同获得ACM图灵奖。他还获得了七个荣誉博士学位。<br/>1981年，Hennessy带领几位研究生在斯坦福大学开始研究MIPS项目。1984年完成该项目后，他暂时离开大学，与他人共同创建了MIPSComputerSystems公司（现在的MIPSTechnologies公司），该公司开发了早期的商用RISC微处理器之一。2006年，已有超过20亿个MIPS微处理器应用在从视频游戏和掌上计算机到激光打印机和网络交换机的各类设备中。Hennessy后来领导了共享存储器体系结构（DASH）项目，该项目设计了第一个可扩展cache一致性多处理器原型，其中的很多关键思想都在现代多处理器中得到了应用。除了参与科研活动和履行学校职责之外，Hennessy还作为前期顾问和投资者参与了很多初创项目，为相关领域学术成果的商业化做出了杰出贡献。<br/>他目前是Knight-Hennessy学者奖学金项目的主管，并担任Alphabet的非执行董事长。
目录
Contents <br /><br />CHAPTERS <br /><br />Computer Abstractions and Technology 2 <br />1.1 Introduction 3 <br />1.2 Seven Great Ideas in Computer Architecture 10 <br />1.3 Below Your Program 13 <br />1.4 Under the Covers 16 <br />1.5 Technologies for Building Processors and Memory 25 <br />1.6 Performance 29 <br />1.7 The Power Wall 40 <br />1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors 43 <br />1.9 Real Stuff: Benchmarking the Intel Core i7 46 <br />1.10 Going Faster: Matrix Multiply in Python 49 <br />1.11 Fallacies and Pitfalls 50 <br /><br />1.12 Concluding Remarks 53 <br />1.13 Historical Perspective and Further Reading 55 <br />1.14 Self-Study 55 <br />1.15 Exercises 59 <br /><br /><br />Instructions: Language of the Computer 66 <br />2.1 Introduction 68 <br />2.2 Operations of the Computer Hardware 69 <br />2.3 Operands of the Computer Hardware 73 <br />2.4 Signed and Unsigned Numbers 80 <br />2.5 Representing Instructions in the Computer 87 <br />2.6 Logical Operations 95 <br />2.7 Instructions for Making Decisions 98 <br />2.8 Supporting Procedures in Computer Hardware 104 <br />2.9 Communicating with People 114 <br />2.10 RISC-V Addressing for Wide Immediates and Addresses 120 <br />2.11 Parallelism and Instructions: Synchronization 128 <br />2.12 Translating and Starting a Program 131 <br />2.13 A C Sort Example to Put it All Together 140 <br /><br /><br /><br /><br /><br /><br />2.14 Arrays versus Pointers 148 <br />2.15 Advanced Material: Compiling C and Interpreting Java 151 <br />2.16 Real Stuff: MIPS Instructions 152 <br />2.17 Real Stuff: ARMv7 (32-bit) Instructions 153 <br />2.18 Real Stuff: ARMv8 (64-bit) Instructions 157 <br />2.19 Real Stuff: x86 Instructions 158 <br />2.20 Real Stuff: The Rest of the RISC-V Instruction Set 167 <br />2.21 Going Faster: Matrix Multiply in C 168 <br />2.22 Fallacies and Pitfalls 170 <br />2.23 Concluding Remarks 172 <br />2.24 Historical Perspective and Further Reading 174 <br />2.25 Self-Study 175 <br />2.26 Exercises 178 <br /><br />Arithmetic for Computers 188 <br />3.1 Introduction 190 <br />3.2 Addition and Subtraction 190 <br />3.3 Multiplication 193 <br />3.4 Division 199 <br />3.5 Floating Point 208 <br />3.6 Parallelism and Computer Arithmetic: Subword Parallelism 233 <br />3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions <br />in x86 234 <br />3.8 Going Faster: Subword Parallelism and Matrix Multiply 236 <br />3.9 Fallacies and Pitfalls 238 <br />3.10 Concluding Remarks 241 <br />3.11 Historical Perspective and Further Reading 242 <br />3.12 Self-Study 242 <br />3.13 Exercises 246 <br /><br />The Processor 252 <br />4.1 Introduction 254 <br />4.2 Logic Design Conventions 258 <br />4.3 Building a Datapath 261 <br />4.4 A Simple Implementation Scheme 269 <br />4.5 Multicycle Implementation 282 <br />4.6 An Overview of Pipelining 283 <br />4.7 Pipelined Datapath and Control 296 <br />4.8 Data Hazards: Forwarding versus Stalling 313 <br />4.9 Control Hazards 325 <br />4.10 Exceptions 333 <br />4.11 Parallelism via Instructions 340 <br />4.12 Putting It All Together: The Intel Core i7 6700 and ARM <br />Cortex-A53 354 <br /><br /><br /><br /><br /><br />4.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply 363 <br />4.14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 365 <br />4.15 Fallacies and Pitfalls 365 <br />4.16 Concluding Remarks 367 <br />4.17 Historical Perspective and Further Reading 368 <br />4.18 Self-Study 368 <br />4.19 Exercises 369 <br /><br />Large and Fast: Exploiting Memory Hierarchy 386 <br />5.1 Introduction 388 <br />5.2 Memory Technologies 392 <br />5.3 The Basics of Caches 398 <br />5.4 Measuring and Improving Cache Performance 412 <br />5.5 Dependable Memory Hierarchy 431 <br />5.6 Virtual Machines 436 <br />5.7 Virtual Memory 440 <br />5.8 A Common Framework for Memory Hierarchy 464 <br />5.9 Using a Finite-State Machine to Control a Simple Cache 470 <br />5.10 Parallelism and Memory Hierarchy: Cache Coherence 475 <br />5.11 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive <br />Disks 479 <br />5.12 Advanced Material: Implementing Cache Controllers 480 <br />5.13 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Memory <br />Hierarchies 480 <br />5.14 Real Stuff: The Rest of the RISC-V System and Special Instructions 486 <br />5.15 Going Faster: Cache Blocking and Matrix Multiply 488 <br />5.16 Fallacies and Pitfalls 489 <br />5.17 Concluding Remarks 494 <br />5.18 Historical Perspective and Further Reading 495 <br />5.19 Self-Study 495 <br />5.20 Exercises 499 <br /><br /><br />Parallel Processors from Client to Cloud 518 <br />6.1 Introduction 520 <br />6.2 The Difficulty of Creating Parallel Processing Programs 522 <br />6.3 SISD, MIMD, SIMD, SPMD, and Vector 527 <br />6.4 Hardware Multithreading 534 <br />6.5 Multicore and Other Shared Memory Multiprocessors 537 <br />6.6 Introduction to Graphics Processing Units 542 <br />6.7 Domain-Specific Architectures 549 <br />6.8 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors 552 <br /><br />6.9 Introduction to Multiprocessor Network Topologies 557 <br />6.10 Communicating to the Outside World: Cluster Networking 561 <br />6.11 Multiprocessor Benchmarks and Performance Models 561 <br />6.12 Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster 572 <br />6.13 Going Faster: Multiple Processors and Matrix Multiply 580 <br />6.14 Fallacies and Pitfalls 583 <br /><br />6.15 Concluding Remarks 585 <br />6.16 Historical Perspective and Further Reading 587 <br />6.17 Self-Study 588 <br />6.18 Exercises 590 <br />APPENDIX <br /><br /><br />The Basics of Logic Design A-2 <br />A.1 Introduction A-3 <br />A.2 Gates, Truth Tables, and Logic Equations A-4 <br />A.3 Combinational Logic A-9 <br />A.4 Using a Hardware Description Language A-20 <br />A.5 Constructing a Basic Arithmetic Logic Unit A-26 <br />A.6 Faster Addition: Carry Lookahead A-37 <br />A.7 Clocks A-47 <br />A.8 Memory Elements: Flip-Flops, Latches, and Registers A-49 <br />A.9 Memory Elements: SRAMs and DRAMs A-57 <br />A.10 Finite-State Machines A-66 <br />A.11 Timing Methodologies A-71 <br />A.12 Field Programmable Devices A-77 <br />A.13 Concluding Remarks A-78 <br />A.14 Exercises A-79 Index I-1 <br />ONLINE CONTENT <br /><br /><br />Graphics and Computing GPUs B-2 <br />B.1 Introduction B-3 <br />B.2 GPU System Architectures B-7 <br />B.3 Programming GPUs B-12 <br />B.4 Multithreaded Multiprocessor Architecture B-25 <br />B.5 Parallel Memory System B-36 <br />B.6 F
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