chapter 1 introduction 1 1.1 digital multiplex concept 1 1.2 digital multiplex hierarchy 3 1.3 ccitt remendations 5 1.4 content of the book 6 chapter 2 synchronous multipleng 7 2.1 synchronous multipleng equipment ition 7 2.2 frame structure 9 2.3 frame alignment 11 2.4 synchronization acquisition method 13 2.5 the code type of frame alignment signals 15 2.6 average acquisition time 16 2.7 optimum length of frame alignment signal 20 2.8 synchromization status protection 24 2.9 acquisition procedure checking 27 2.10 frame alignment protection parameters 31 2.11 average out-of-frame time and average synchronization time 34 2.12 the bit errors of synchronization out-of-frame 35 2.13 frame alignment acquisition/ maintenance logic 37 2.14 guaranteeing the synchronization circumstance 41 2.15 ccitt remendations 44 chapter 3 itive justification 49 3.1 plesiochronous multiplex 49 3.2 principle of itive justification 50 3.3 basic formula of itive justification 52 3.4 justification design 54 3.5 justification transition process 57 3.6 the change range of the read/write time difference in a stable justification process 61 3.7 classification of justification transition process 64 3.8 bit rate recovery design 66 3.9 phase-lock parameters design 69 3.10 voltage controlled oscillator design 73 3.11 buffer size 76 3.12 ccitt remendations 78 chapter 4 impairment of itive justification 82 4.1 stuffing jitter 82 4.1.1 physical concept of stuffing jitter 82 4.1.2 signal justification process justifying only q times in p frames 84 4.1.3 justifying q times in p frames with a residue 88 4.1.4 the relationship between the number of code justification detectors and stuffing jitter 95 4.1.5 distribution of stuffing jitter 99 4.2 stuffing error 104 4.2.1 physical concept of stuffing error 104 4.2.2 calculation of stuffing error 104 4.2.3 suppression of stuffing errors 109 chapter 5 itive/ justification 111 5.1 the principle of itive/ justification 111 5.2 justification by fix ed decision control 113 5.3 adaptive justification control 116 5.4 itive/ justification control circuit 124 5.5 transition process of justification 126 5.6 parameter design of justification 128 5.7 environment design of justification 131 5.8 the technical application of the itive/ justification 135 5.9 example of itive/ justification design 136 5.10 characteristic paison of justifications 142 5.11 remendation of ccitt 143 chapter 6 itive/0/ justification 145 6.1 concept of itive/0/ justification 145 6.2 the principles of delta controlled itive/0/ justification 146 6.3 digital smooth itive/0/ justification principles 147 6.4 frame structure 149 6.5 justification and recovery control 153 6.6 justification transition process 156 6.7 digital smooth 162 6.8 pulse smoothly principle of west german pcm30d 163 6.9 australla 2/8mbit/s multiplexer pulse smooth principle 166 6.10 engineering applications of itive/0/ justification 169 chapter 7 measurement techniques of justification 170 7.1 measurement of stuffing jitter 170 7.1.1 characteristics of stuffing jitter 170 7.1.2 measurement range and precision requirement 172 7.1.3 measurement equipment 173 7.1.4 measurement method 176 7.1.5 example of measurement 181 7.2 measurement of multiplex code error 183 7.2.1 characteristics of multiplex code error 183 7.2.2 requirements of code error meter 184 7.2.3 design of spe code error meter 186 7.2.4 design of analog channel 189 7.2.5 example of measurement 190 7.3 measurement characteristics of the phase-locked loop of the code recovery 192 7.3.1 tracing error measurement 192 7.3.2 measurement of jitter suppression characteristics 194 chapter 8 frame adjustment principle 195 8.1 general 195 8.2 frame regulation categories 198 8.3 the working principle of pre-buffer frame regulator 199 8.4 2048kbit/s frame regulator design 203 8.5 the additional function of frame regulator 210 chapter 9 pdh/sdh interface 211 9.1 general 211 9.2 higher order group sdh 211 9.3 the general arrangement of pdh/sdh interface 214 9.4 the arrangement design for c-4 to enter stm-1 217 9.5 the arrangement design for c-3 entering stm-1 221 9.6 the arrangement design for tug entering high order vc 224 9.7 basic container entering tug 227 9.8 stm-n multipleng 231 9.9 payload container interface in ccitt rec 234 9.10 the improved design of payload container interface 240 chapter 10 anti fa frame synchronization 248 10.1 the principles of anti fa frame synchronization 248 10.2 frame synchronization average keeping time 253 10.2.1 scheme (1) 253 10.2.2 scheme (2) 255 10.2.3 scheme (3) 257 10.2.4 scheme (4) 261 10.2.5 scheme (5) 265 10.2.6 scheme (6) 269 10.3 frame loss average keeping time 273 10.3.1 frame loss deci time 273 10.3.2 frame synchronization search time 275 10.3.3 frame synchronization deci time 278 10.3.4 frame synchronization reset delay 285 10.3.5 frame loss keeping time 286 10.4 parison of frame synchronization schemes 286 10.4.1 frame synchronization average keeping time 286 10.4.2 frame loss average keeping time 289 10.4.3 the synthetical criterion of the frame synchronization system 293 chapter 11 engineering application design 296 11.1 general plesiochronous group multiplex design 296 11.1.1 elementary parameters design 296 11.1.2 transition process design 300 11.1.3 frame loss probability and search characteristics design 300 11.1.4 partition of the basic units 301 11.1.5 design examples 302 11.2 standard/non-standard rates tolerance design 307 11.2.1 introduction 307 11.2.2 transmission of non-standard binary digits through standard channels 308 11.2.3 design examples 309 11.2.4 patible multiplex of different tributary rates 310 11.3 plesiochronous/synchronous patible design 313 11.3.1 introduction 313 11.3.2 instruction justification patible method 313 11.3.3 multiframe fixed control patible method 316 11.4 2/
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