计算机组成与嵌入式系统
￥ 12.19 1.8折 ￥ 69 九五品
仅1件
北京海淀
认证卖家担保交易快速发货售后保障
作者哈马克 (Carl Hamacher)
出版社机械工业出版社
ISBN9787111377214
出版时间2013-01
版次1
装帧平装
开本16开
纸张胶版纸
页数710页
定价69元
上书时间2024-07-09
商品详情
- 品相描述：九五品
- 商品描述
-
基本信息
书名:计算机组成与嵌入式系统
定价：69.00元
作者:哈马克 (Carl Hamacher)
出版社：机械工业出版社
出版日期：2013-01-01
ISBN：9787111377214
字数：
页码：710
版次：1
装帧：平装
开本：16开
商品重量：
编辑推荐
Carl Hamacher,Zvonko Vranesic,Safwat
Zaky,Naraig
Manjikian所著的《计算机组成与嵌入式系统(英文版第6版)》系统地介绍了现代计算机硬件系统的各个组成部分，包括处理器、输入／输出、存储器和互连标准等。以Nios
II、ARM、ColdFire和Intel
IA-32等商用处理器为例来阐释基本概念，侧重于讨论RISC设计风格的处理器(如MIPS)，同时也介绍了CISC设计风格的处理器(如应用比较广泛的商用处理器InlelIA-32)。
内容提要
《计算机组成与嵌入式系统(英文版·第6版)》是一本经典的计算机组成教材，自1978年问世以来，已被多所世界知名大学选为教材。《计算机组成与嵌入式系统(英文版·第6版)》知识结构合理，知识点全面完整，基本概念广泛而新颖。书中不仅介绍了硬件设计的原理，说明了硬件设计如何受软件需求影响，而且以流行的商用处理器作为范例，描述了各种基本知识和基本概念的应用方法和应用过程，具有很强的实用性。此外，《计算机组成与嵌入式系统(英文版·第6版)》还涵盖了当今许多先进的技术和设计思想。
目录
ContentsChapter 1 Basic Structure of Computers1.1 Computer Types1.2 Functional Units1.2.1 Input Unit1.2.2 Memory Unit1.2.3 Arithmetic and Logic Unit1.2.4 Output Unit1.2.5 Control UnitProblemsReferencesChapter 2 InstructioSet Architecture2.1 Memory Locations and Addresses2.1.1 Byte Addressability2.1.2 Big-Endiaand Little-EndiaAssignments2.1.3 Word Alignment2.1.4 Accessing Numbers and Characters2.2 Memory Operations2.3 Instructions and InstructioSequencing2.3.1 Register Transfer Notation2.3.2 Assembly-Language Notation2.3.3 RISC and CISC InstructioSets2.3.4 Introductioto RISC InstructioSets2.3.5 InstructioExecutioand Straight-Line Sequencing2.3.6 Branching2.3.7 Generating Memory Addresses2.4 Addressing Modes2.4.1 Implementatioof Variables and Constants2.4.2 Indirectioand Pointers2.4.3 Indexing and Arrays2.5 Assembly Language2.5.1 Assembler Directives2.5.2 Assembly and Executioof Programs2.5.3 Number Notation2.6 Stacks2.7 Subroutines2.7.1 Subroutine Nesting and the Processor Stack2.7.2 Parameter Passing2.7.3 The Stack Frame2.8 Additional Instructions2.8.1 Logic Instructions2.8.2 Shift and Rotate Instructions2.8.3 Multiplicatioand Division2.9 Dealing with 32-Bit Immediate Values2.10 CISC InstructioSets2.10.1 Additional Addressing Modes2.10.2 ConditioCodes2.11 RISC and CISC Styles2.12 Example Programs2.12.1 Vector Dot Product Program2.12.2 String Search Program2.13 Encoding of Machine Instructions2.14 Concluding RemarksProblemsChapter 3 Basic Input/Output3.1 Accessing I/O Devices3.1.1 I/O Device Interface3.1.2 Program-Controlled I/O3.1.3 AExample of a RISC-Style I/O Program3.1.4 AExample of a CISC-Style I/O Program3.2 Interrupts3.2.1 Enabling and Disabling Interrupts3.2.2 Handling Multiple Devices3.2.3 Controlling I/O Device Behavior3.2.4 Processor Control Registers3.2.5 Examples of Interrupt Programs3.2.6 Exceptions3.3 Concluding RemarksProblemsChapter 4 Software4.1 The Assembly Process4.1.1 Two-pass Assembler4.2 Loading and Executing Object Programs4.3 The Linker4.4 Libraries4.5 The Compiler4.5.1 Compiler Optimizations4.5.2 Combining Programs WritteiDifferent Languages4.6 The Debugger4.7 Using a High-level Language for I/O Tasks4.8 InteractiobetweeAssembly Language and C Language4.9 The Operating System4.9.1 The Boot-strapping Process4.9.2 Managing the Executioof ApplicatioPrograms4.9.3 Use of Interrupts iOperating Systems4.10 Concluding RemarksProblemsReferencesChapter 5 Basic Processing Unit5.1 Some Fundamental Concepts5.2 InstructioExecution5.2.1 Load Instructions5.2.2 Arithmetic and Logic Instructions5.2.3 Store Instructions5.3 Hardware Components5.3.1 Register File5.3.2 ALU5.3.3 Datapath5.3.4 InstructioFetch Section5.4 InstructioFetch and ExecutioSteps5.4.1 Branching5.4.2 Waiting for Memory5.5 Control Signals5.6 Hardwired Control5.6.1 Datapath Control Signals5.6.2 Dealing with Memory Delay5.7 CISC-Style Processors5.7.1 AInterconnect using Buses5.7.2 Microprogrammed Control5.8 Concluding RemarksProblemsChapter 6 Pipelining6.1 Basic Concept桾he Ideal Case6.2 Pipeline Organization6.3 Pipelining Issues6.4 Data Dependencies6.4.1 Operand Forwarding6.4.2 Handling Data Dependencies iSoftware6.5 Memory Delays6.6 Branch Delays6.6.1 Unconditional Branches6.6.2 Conditional Branches6.6.3 The Branch Delay Slot6.6.4 Branch Prediction6.7 Resource Limitations6.8 Performance Evaluation6.8.1 Effects of Stalls and Penalties6.8.2 Number of Pipeline Stages6.9 Superscalar Operation6.9.1 Branches and Data Dependencies6.9.2 Out-of-Order Execution6.9.3 ExecutioCompletion6.9.4 Dispatch OperationProblemsReferencesChapter 7 Input/Output Organization7.1 Bus Structure7.2 Bus Operation7.2.1 Synchronous Bus7.2.2 Asynchronous Bus7.2.3 Electrical Considerations7.3 Arbitration7.4 Interface Circuits7.4.1 Parallel Interface7.4.2 Serial Interface7.5 InterconnectioStandards7.5.1 Universal Serial Bus (USB)7.5.2 FireWire7.5.3 PCI Bus7.5.4 SCSI Bus7.5.5 SATA7.5.6 SAS7.5.7 PCI Express7.6 Concluding RemarksProblemsReferencesChapter 8 The Memory System8.1 Basic Concepts8.2 Semiconductor RAM Memories8.2.1 Internal Organizatioof Memory Chips8.2.2 Static Memories8.2.3 Dynamic RAMs8.2.4 Synchronous DRAMs8.2.5 Structure of Larger Memories8.3 Read-only Memories8.3.1 ROM8.3.2 PROM8.3.3 EPROM8.3.4 EEPROM8.3.5 Flash Memory8.4 Direct Memory Access8.5 Memory Hierarchy8.6 Cache Memories8.6.1 Mapping Functions8.6.2 Replacement Algorithms8.6.3 Examples of Mapping Techniques8.7 Performance Considerations8.7.1 Hit Rate and Miss Penalty8.7.2 Caches othe Processor Chip8.7.3 Other Enhancements8.8 Virtual Memory8.8.1 Address TranslationProblemsReferencesChapter 9 Arithmetic9.1 Additioand Subtractioof Signed Numbers9.1.1 Addition/SubtractioLogic Unit9.2 Desigof Fast Adders9.2.1 Carry-Lookahead Addition9.3 Multiplicatioof Unsigned Numbers9.3.1 Array Multiplier9.3.2 Sequential Circuit Multiplier9.4 Multiplicatioof Signed Numbers9.4.1 The Booth Algorithm9.5 Fast Multiplication9.5.1 Bit-Pair Recoding of Multipliers9.5.2 Carry-Save Additioof Summands9.5.3 Summand AdditioTree using 3-2 Reducers9.5.4 Summand AdditioTree using 4-2 Reducers9.5.5 Summary of Fast Multiplication9.6 Integer Division9.7 Floating-Point Numbers and Operations9.7.1 Arithmetic Operations oFloating-Point Numbers9.7.2 Guard Bits and Truncation9.7.3 Implementing Floating-Point OperationsProblemsReferencesChapter 10 Parallel Processing and Performance10.1 Hardware Multithreading10.2 Vector (SIMD) Processing10.2.1 Graphics Processing Units (GPUs)10.3 Shared-Memory Multiprocessors10.3.1 InterconnectioNetworks10.4 Cache Coherence10.4.1 Write-Through Protocol10.4.2 Write-Back protocol10.4.3 Snoopy Caches10.4.4 Directory-Based Cache Coherence10.5 Message-Passing Multicomputers10.6 Parallel Programming for Multiprocessors10.7 Performance Modeling10.8 Concluding RemarksProblemsReferencesAppendix ALogic CircuitsA.1 Basic Logic FunctionsA.1.1 Electronic Logic GatesA.2 Synthesis of Logic FunctionsA.3 Minimizatioof Logic ExpressionsA.3.1 Minimizatiousing Karnaugh MapsA.3.2 Don抰-Care ConditionsA.4 Synthesis with NAND and NOR GatesA.5 Practical Implementatioof Logic GatesA.5.1 CMOS CircuitsA.5.2 PropagatioDelayA.5.3 Fan-Iand Fan-Out ConstraintsA.5.4 Tri-State BuffersA.6 Flip-FlopsA.6.1 Gated LatchesA.6.2 Master-Slave Flip-FlopA.6.3 Edge TriggeringA.6.4 T Flip-FlopA.6.5 JK Flip-FlopA.6.6 Flip-Flops with Preset and ClearA.7 Registers and Shift RegistersA.8 CountersA.9 DecodersA.10 MultiplexersA.11 Concluding RemarksProblemsReferencesAppendix BThe Intel IA-32 ArchitectureB.1 Memory OrganizationB.2 Register StructureB.3 Addressing ModesB.4 InstructionsB.4.1 Machine InstructioFormatB.4.2 Assembly-Language NotationB.4.3 Move InstructionB.4.4 Load-Effective-Address InstructionB.4.5 Arithmetic InstructionsB.4.6 Jump and Loop InstructionsB.4.7 Logic InstructionsB.4.8 Shift and Rotate InstructionsB.4.9 Subroutine Linkage InstructionsB.4.10 Operations oLarge NumbersB.5 Assembler DirectivesB.6 Example ProgramsB.6.1 Vector Dot Product ProgramB.6.2 String Search ProgramB.7 Interrupts and ExceptionsB.8 Input/Output ExamplesB.9 Scalar Floating-Point OperationsB.9.1 Load and Store InstructionsB.9.2 Arithmetic InstructionsB.9.3 ComparisoInstructionsB.9.4 Additional InstructionsB.9.5 Example Floating-Point ProgramB.10 Multimedia Extensio(MMX) OperationsB.11 Vector (SIMD) Floating-Point OperationsB.12 Concluding RemarksProblemsReferences
作者介绍
序言
-
【封面】
— 没有更多了 —
以下为对购买帮助不大的评价