计算机组成与嵌入式系统（英文版 第6版）

图书标准信息

• 作者 [加]Zvonko、Safwat、Naraig Manjikian 著
• 出版社 机械工业出版社
• 出版时间 2012-12
• 版次 6
• ISBN 9787111377214
• 定价 69.00元
• 装帧 平装
• 开本 32开
• 纸张 胶版纸
• 正文语种 英语
• 原版书名 Computer Organizationand and Embedded Systems, Sixth Edition
• 丛书 经典原版书库

【内容简介】

　　《经典原版书库：计算机组成（英文版·第6版）》是一本经典的计算机组成教材，自1978年问世以来，已被多所世界知名大学选为教材。《经典原版书库：计算机组成（英文版·第6版）》知识结构合理，知识点全面完整，基本概念广泛而新颖。《经典原版书库：计算机组成（英文版·第6版）》中不仅介绍了硬件设计的原理，说明了硬件设计如何受软件需求影响，而且以流行的商用处理器作为范例，描述了各种基本知识和基本概念的应用方法和应用过程，具有很强的实用性。此外，《经典原版书库：计算机组成（英文版·第6版）》还涵盖了当今许多先进的技术和设计思想。

【作者简介】

     Zvonko Vranesic多伦多大学电气与计算机工程系教授，同时参与AItera公司多伦多技术中心的研究和开发工作。他代表加拿大参加过多次国际象棋比赛。拥有国际象棋大师的头衔。目前他的研究兴趣包括：计算机体系结构、现场可编程超大规模集成电路技术和多值逻辑系统。CarlHamacher加拿大女皇大学电子工程与计算机系荣誉退休教授，曾担任女皇大学应用科学系主任。多伦多大学电子工程及计算机科学系教授、计算机系统研究所所长、工程科学部主席。他的研究兴趣是多处理器和多计算机，侧重于网络互连。SafwatZaky加拿大多伦多大学电气与计算机工程系荣誉退休教授。曾担任该系系主任。他的研究兴趣是计算机体系结构、数字电路设计和电磁兼容性。NaraigManjikian加拿大女皇大学电子工程与计算机系副教授。他的研究兴趣是计算机体系结构、多处理器系统、现场可编程超大规模集成电路技术和并行处理技术应用。

【目录】

Contents
Chapter1BasicStructureofComputers
1.1ComputerTypes
1.2FunctionalUnits
1.2.1InputUnit
1.2.2MemoryUnit
1.2.3ArithmeticandLogicUnit
1.2.4OutputUnit
1.2.5ControlUnit
Problems
References

Chapter2InstructionSetArchitecture
2.1MemoryLocationsandAddresses
2.1.1ByteAddressability
2.1.2Big-EndianandLittle-EndianAssignments
2.1.3WordAlignment
2.1.4AccessingNumbersandCharacters
2.2MemoryOperations
2.3InstructionsandInstructionSequencing
2.3.1RegisterTransferNotation
2.3.2Assembly-LanguageNotation
2.3.3RISCandCISCInstructionSets
2.3.4IntroductiontoRISCInstructionSets
2.3.5InstructionExecutionandStraight-LineSequencing
2.3.6Branching
2.3.7GeneratingMemoryAddresses
2.4AddressingModes
2.4.1ImplementationofVariablesandConstants
2.4.2IndirectionandPointers
2.4.3IndexingandArrays
2.5AssemblyLanguage
2.5.1AssemblerDirectives
2.5.2AssemblyandExecutionofPrograms
2.5.3NumberNotation
2.6Stacks
2.7Subroutines
2.7.1SubroutineNestingandtheProcessorStack
2.7.2ParameterPassing
2.7.3TheStackFrame
2.8AdditionalInstructions
2.8.1LogicInstructions
2.8.2ShiftandRotateInstructions
2.8.3MultiplicationandDivision
2.9Dealingwith32-BitImmediateValues
2.10CISCInstructionSets
2.10.1AdditionalAddressingModes
2.10.2ConditionCodes
2.11RISCandCISCStyles
2.12ExamplePrograms
2.12.1VectorDotProductProgram
2.12.2StringSearchProgram
2.13EncodingofMachineInstructions
2.14ConcludingRemarks
Problems

Chapter3BasicInput/Output
3.1AccessingI/ODevices
3.1.1I/ODeviceInterface
3.1.2Program-ControlledI/O
3.1.3AnExampleofaRISC-StyleI/OProgram
3.1.4AnExampleofaCISC-StyleI/OProgram
3.2Interrupts
3.2.1EnablingandDisablingInterrupts
3.2.2HandlingMultipleDevices
3.2.3ControllingI/ODeviceBehavior
3.2.4ProcessorControlRegisters
3.2.5ExamplesofInterruptPrograms
3.2.6Exceptions
3.3ConcludingRemarks
Problems

Chapter4Software
4.1TheAssemblyProcess
4.1.1Two-passAssembler
4.2LoadingandExecutingObjectPrograms
4.3TheLinker
4.4Libraries
4.5TheCompiler
4.5.1CompilerOptimizations
4.5.2CombiningProgramsWritteninDifferentLanguages
4.6TheDebugger
4.7UsingaHigh-levelLanguageforI/OTasks
4.8InteractionbetweenAssemblyLanguageandCLanguage
4.9TheOperatingSystem
4.9.1TheBoot-strappingProcess
4.9.2ManagingtheExecutionofApplicationPrograms
4.9.3UseofInterruptsinOperatingSystems
4.10ConcludingRemarks
Problems
References

Chapter5BasicProcessingUnit
5.1SomeFundamentalConcepts
5.2InstructionExecution
5.2.1LoadInstructions
5.2.2ArithmeticandLogicInstructions
5.2.3StoreInstructions
5.3HardwareComponents
5.3.1RegisterFile
5.3.2ALU
5.3.3Datapath
5.3.4InstructionFetchSection
5.4InstructionFetchandExecutionSteps
5.4.1Branching
5.4.2WaitingforMemory
5.5ControlSignals
5.6HardwiredControl
5.6.1DatapathControlSignals
5.6.2DealingwithMemoryDelay
5.7CISC-StyleProcessors
5.7.1AnInterconnectusingBuses
5.7.2MicroprogrammedControl
5.8ConcludingRemarks
Problems

Chapter6Pipelining
6.1BasicConcept桾heIdealCase
6.2PipelineOrganization
6.3PipeliningIssues
6.4DataDependencies
6.4.1OperandForwarding
6.4.2HandlingDataDependenciesinSoftware
6.5MemoryDelays
6.6BranchDelays
6.6.1UnconditionalBranches
6.6.2ConditionalBranches
6.6.3TheBranchDelaySlot
6.6.4BranchPrediction
6.7ResourceLimitations
6.8PerformanceEvaluation
6.8.1EffectsofStallsandPenalties
6.8.2NumberofPipelineStages
6.9SuperscalarOperation
6.9.1BranchesandDataDependencies
6.9.2Out-of-OrderExecution
6.9.3ExecutionCompletion
6.9.4DispatchOperation
Problems
References

Chapter7Input/OutputOrganization
7.1BusStructure
7.2BusOperation
7.2.1SynchronousBus
7.2.2AsynchronousBus
7.2.3ElectricalConsiderations
7.3Arbitration
7.4InterfaceCircuits
7.4.1ParallelInterface
7.4.2SerialInterface
7.5InterconnectionStandards
7.5.1UniversalSerialBus(USB)
7.5.2FireWire
7.5.3PCIBus
7.5.4SCSIBus
7.5.5SATA
7.5.6SAS
7.5.7PCIExpress
7.6ConcludingRemarks
Problems
References

Chapter8TheMemorySystem
8.1BasicConcepts
8.2SemiconductorRAMMemories
8.2.1InternalOrganizationofMemoryChips
8.2.2StaticMemories
8.2.3DynamicRAMs
8.2.4SynchronousDRAMs
8.2.5StructureofLargerMemories
8.3Read-onlyMemories
8.3.1ROM
8.3.2PROM
8.3.3EPROM
8.3.4EEPROM
8.3.5FlashMemory
8.4DirectMemoryAccess
8.5MemoryHierarchy
8.6CacheMemories
8.6.1MappingFunctions
8.6.2ReplacementAlgorithms
8.6.3ExamplesofMappingTechniques
8.7PerformanceConsiderations
8.7.1HitRateandMissPenalty
8.7.2CachesontheProcessorChip
8.7.3OtherEnhancements
8.8VirtualMemory
8.8.1AddressTranslation
Problems
References

Chapter9Arithmetic
9.1AdditionandSubtractionofSignedNumbers
9.1.1Addition/SubtractionLogicUnit
9.2DesignofFastAdders
9.2.1Carry-LookaheadAddition
9.3MultiplicationofUnsignedNumbers
9.3.1ArrayMultiplier
9.3.2SequentialCircuitMultiplier
9.4MultiplicationofSignedNumbers
9.4.1TheBoothAlgorithm
9.5FastMultiplication
9.5.1Bit-PairRecodingofMultipliers
9.5.2Carry-SaveAdditionofSummands
9.5.3SummandAdditionTreeusing3-2Reducers
9.5.4SummandAdditionTreeusing4-2Reducers
9.5.5SummaryofFastMultiplication
9.6IntegerDivision
9.7Floating-PointNumbersandOperations
9.7.1ArithmeticOperationsonFloating-PointNumbers
9.7.2GuardBitsandTruncation
9.7.3ImplementingFloating-PointOperations
Problems
References

Chapter10ParallelProcessingandPerformance
10.1HardwareMultithreading
10.2Vector(SIMD)Processing
10.2.1GraphicsProcessingUnits(GPUs)
10.3Shared-MemoryMultiprocessors
10.3.1InterconnectionNetworks
10.4CacheCoherence
10.4.1Write-ThroughProtocol
10.4.2Write-Backprotocol
10.4.3SnoopyCaches
10.4.4Directory-BasedCacheCoherence
10.5Message-PassingMulticomputers
10.6ParallelProgrammingforMultiprocessors
10.7PerformanceModeling
10.8ConcludingRemarks
Problems
References

AppendixALogicCircuits
A.1BasicLogicFunctions
A.1.1ElectronicLogicGates
A.2SynthesisofLogicFunctions
A.3MinimizationofLogicExpressions
A.3.1MinimizationusingKarnaughMaps
A.3.2Don抰-CareConditions
A.4SynthesiswithNANDandNORGates
A.5PracticalImplementationofLogicGates
A.5.1CMOSCircuits
A.5.2PropagationDelay
A.5.3Fan-InandFan-OutConstraints
A.5.4Tri-StateBuffers
A.6Flip-Flops
A.6.1GatedLatches
A.6.2Master-SlaveFlip-Flop
A.6.3EdgeTriggering
A.6.4TFlip-Flop
A.6.5JKFlip-Flop
A.6.6Flip-FlopswithPresetandClear
A.7RegistersandShiftRegisters
A.8Counters
A.9Decoders
A.10Multiplexers
A.11ConcludingRemarks
Problems
References

AppendixBTheIntelIA-32Architecture
B.1MemoryOrganization
B.2RegisterStructure
B.3AddressingModes
B.4Instructions
B.4.1MachineInstructionFormat
B.4.2Assembly-LanguageNotation
B.4.3MoveInstruction
B.4.4Load-Effective-AddressInstruction
B.4.5ArithmeticInstructions
B.4.6JumpandLoopInstructions
B.4.7LogicInstructions
B.4.8ShiftandRotateInstructions
B.4.9SubroutineLinkageInstructions
B.4.10OperationsonLargeNumbers
B.5AssemblerDirectives
B.6ExamplePrograms
B.6.1VectorDotProductProgram
B.6.2StringSearchProgram
B.7InterruptsandExceptions
B.8Input/OutputExamples
B.9ScalarFloating-PointOperations
B.9.1LoadandStoreInstructions
B.9.2ArithmeticInstructions
B.9.3ComparisonInstructions
B.9.4AdditionalInstructions
B.9.5ExampleFloating-PointProgram
B.10MultimediaExtension(MMX)Operations
B.11Vector(SIMD)Floating-PointOperations
B.12ConcludingRemarks
Problems
References