VerilogHDL高级数字设计英文版

图书标准信息

• 作者 [美]西勒提 著
• 出版社 电子工业出版社
• 出版时间 2010-04
• 版次 1
• ISBN 9787121104770
• 定价 98.00元
• 装帧 平装
• 开本 16开
• 纸张 胶版纸
• 页数 965页
• 字数 1813千字
• 正文语种 英语
• 丛书 国外电子与通信教材系列

【内容简介】

《VerilogHDL高级数字设计（第2版）（英文版）》依据数字集成电路系统工程开发的要求与特点，利用VerilogHDL对数字系统进行建模、设计与验证，对ASIC/FPGA系统芯片工程设计开发的关键技术与流程进行了深入讲解，内容包括：集成电路芯片系统的建模、电路结构权衡、流水、多核微处理器、功能验证、时序分析、测试平台、故障模拟、可测性设计、逻辑综合、后综合验证等集成电路系统的前后端工程设计与实现中的关键技术及设计案例。书中以大量设计实例叙述了集成电路系统工程开发需遵循的原则、基本方法、实用技术、设计经验与技巧。
《VerilogHDL高级数字设计（第2版）（英文版）》既可作为电子与通信、电子科学与技术、自动控制、计算机等专业领域的高年级本科生和研究生的教材或参考资格，也可用于电子系统设计及数字集成电路设计工程师的专业技术培训。

【作者简介】

西勒提（MichaelD.Ciletti），科罗拉多大学电气与计算机工程系教授。研究方向包括通过硬件描述语言进行数字系统的建模、综合与验证、系统级设计语言和FPGA嵌入式系统。其著作还有DigitalDesign，FourthEdition（其翻译版和影印版均由电子工业出版社出版）。作者曾在惠普、福特微电子和Prisma等公司进行VLSI电路设计的研发工作，在数字系统和嵌入式系统研究、设计等领域有丰富的研发和教学经历。

【目录】

1IntroductiontoDigitalDesignMethodology
1.1DesignMethodology-AnIntroduction
1.1.1DesignSpecification
1.1.2DesignPartition
1.1.3DesignEntry
1.1.4SimulationandFunctionalVerification
1.1.5DesignIntegrationandVerification
1.1.6PresynthesisSign-Off
1.1.7Gate-LevelSynthesisandTechnologyMapping
1.1.8PostsynthesisDesignValidation
1.1.9PostsynthesisTimingVerification
1.1.10TestGenerationandFaultSimulation
1.1.11PlacementandRouting
1.1.12PhysicalandElectricalDesignRuleChecks
1.1.13ParasiticExtraction
1.1.14DesignSign-Off
1.2ICTechnologyOptions
1.3Overview
References

2ReviewofCombinationalLogicDesign
2.1CombinationalLogicandBooleanAlgebra
2.1.1ASICLibraryCells
2.1.2BooleanAlgebra
2.1.3DeMorgansLaws
2.2TheoremsforBooleanAlgebraicMinimization
2.3RepresentationofCombinationalLogic
2.3.1Sum-of-ProductsRepresentation
2.3.2Product-of-SumsRepresentation
2.4SimplificationofBooleanExpressions
2.4.1SimplificationwithExclusive-Or
2.4.2KarnaughMaps（SOPForm)
2.4.3KarnaughMaps（POSForm)
2.4.4KarnaughMapsandDont-Cares
2.4.5ExtendedKarnaughMaps
2.5GlitchesandHazards
2.5.1EliminationofStaticHazards（SOPForm)
2.5.2Summary:EliminationofStaticHazardsinTwo-LevelCircuits
2.5.3StaticHazardsinMultilevelCircuits
2.5.4Summary:EliminationofStaticHazardsinMultilevelCircuits
2.5.5DynamicHazards
2.6BuildingBlocksforLogicDesign
2.6.1NAND-NORStructures
2.6.2Multiplexers
2.6.3Demultiplexers
2.6.4Encoders
2.6.5PriorityEncoder
2.6.6Decoder
2.6.7PriorityDecoder
References
Problems

3FundamentalsofSequentialLogicDesign
3.1StorageElements
3.1.1Latches
3.1.2TransparentLatches
3.2Flip-Flops
3.2.1D-TypeFlip-Flop
3.2.2Master-SlaveFlip-Flop
3.2.3J-KFlip-Flops
3.2.4TFlip-Flop
3.3BussesandThree-StateDevices
3.4DesignofSequentialMachines
3.5State-TransitionGraphs
3.6DesignExample:BCDtoExcess-3CodeConverter
3.7Serial-LineCodeConverterforDataTransmission
3.7.1DesignExample:AMealy-TypeFSMforSerialLine-CodeConversion
3.7.2DesignExample:AMoore-TypeFSMforSerialLine-CodeConversion
3.8StateReductionandEquivalentStates
References
Problems

4IntroductiontoLogicDesignwithVerilog
4.1StructuralModelsofCombinationalLogic
4.1.1VerilogPrimitivesandDesignEncapsulation
4.1.2VerilogStructuralModels
4.1.3ModulePorts
4.1.4SomeLanguageRules
4.1.5Top-DownDesignandNestedModules
4.1.6DesignHierarchyandSource-CodeOrganization
4.1.7VectorsinVerilog
4.1.8StructuralConnectivity
4.2LogicSystem,DesignVerification,andTestMethodology
4.2.1Four-ValueLogicandSignalResolutioninVerilog
4.2.2TestMethodology
4.2.3SignalGeneratorsforTestbenches
4.2.4Event-DrivenSimulation
4.2.5TestbenchTemplate
4.2.6SizedNumbers
4.3PropagationDelay
4.3.1InertialDelay
4.3.2TransportDelay
4.4TruthTableModelsofCombinationalandSequentialLogicwithVerilog
References
Problems

5LogicDesignwithBehavioralModelsofCombinationalandSequentialLogic
5.1BehavioralModeling
5.2ABriefLookatDataTypesforBehavioralModeling
5.3BooleanEquation-BasedBehavioralModelsofCombinationalLogic
5.4PropagationDelayandContinuousAssignments
5.5LatchesandLevel-SensitiveCircuitsinVerilog
5.6CyclicBehavioralModelsofFlip-FlopsandLatches
5.7CyclicBehaviorandEdgeDetection
5.8AComparisonofStylesforBehavioralModeling
5.8.1ContinuousAssignmentModels
5.8.2Dataflow/RTLModels
5.8.3Algorithm-BasedModels
5.8.4NamingConventions:AMatterofStyle
5.8.5SimulationwithBehavioralModels
5.9BehavioralModelsofMultiplexers,Encoders,andDecoders
5.10DataflowModelsofaLinear-FeedbackShiftRegister
5.11ModelingDigitalMachineswithRepetitiveAlgorithms
5.11.1IntellectualPropertyReuseandParameterizedModels
5.11.2ClockGenerators
5.12MachineswithMulticycleOperations
5.13DesignDocumentationwithFunctionsandTasks:LegacyorLunacy?
5.13.1Tasks
5.13.2Functions
5.14AlgorithmicStateMachineChartsforBehavioralModeling
5.15ASMDCharts
5.16BehavioralModelsofCounters,ShiftRegisters,andRegisterFiles
5.16.1Counters
5.16.2ShiftRegisters
5.16.3RegisterFilesandArraysofRegisters（Memories)
5.17SwitchDebounce,Metastability,andSynchronizersforAsynchronousSignals
5.18DesignExample:KeypadScannerandEncoder
References
Problems

6SynthesisofCombinationalandSequentialLogic
6.1IntroductiontoSynthesis
6.1.1LogicSynthesis
6.1.2RTLSynthesis
6.1.3High-LevelSynthesis
6.2SynthesisofCombinationalLogic
6.2.1SynthesisofPriorityStructures
6.2.2ExploitingLogicalDont-CareConditions
6.2.3ASICCellsandResourceSharing
6.3SynthesisofSequentialLogicwithLatches
6.3.1AccidentalSynthesisofLatches
6.3.2IntentionalSynthesisofLatches
6.4SynthesisofThree-StateDevicesandBusInterfaces
6.5SynthesisofSequentialLogicwithFlip-Flops
6.6SynthesisofExplicitStateMachines
6.6.1SynthesisofaBCD-to-Excess-3CodeConverter
6.6.2DesignExample:SynthesisofaMealy-TypeNRZ-to-ManchesterLineCodeConverter
6.6.3DesignExample:SynthesisofaMoore-TypeNRZ-to-ManchesterLineCodeConverter
6.6.4DesignExample:SynthesisofaSequenceRecognizer
6.7RegisteredLogic
6.8StateEncoding
……
7DesignandSynthesisofDatapathControllers
8ProgrammableLogicandStorageDevices
9AlgorithmsandArchitecturesforDigitalProcessors
10ArchitecturesforArithmeticProcessors
11PostsynthesisDesignTasks
AVerilogPrimitives
BVerilogKeywords
CVerilogDataTypes
DVerilogOperators
EVerilogLanguageFormalSyntax
FVerilogLanguageFormalSyntax
GAdditionalFeaturesofVerilog
HFlip-FlopandLatchTypes
IVerilog-2001,2005
JProgrammingLanguageInterface
KWebsites
LWeb-BasedResources
Index