目录 Preface 1 3D Integration for Semiconductor IC Packaging 1.1 Introduction 1.2 3D Integration 1.3 3D IC Packaging 1.4 3D Si Integration 1.5 3D IC Integration 1.5.1 Hybrid Memory Cube 1.5.2 Wide I/O DRAM and Wide I/O 2 1.5.3 High Bandwidth Memory 1.5.4 Wide I/O Memory (or Logic-on-Logic) 1.5.5 Passive Interposer (2.5D IC Integration) 1.6 Supply Chains before the TSV Era 1.6.1 FEOL (Front-End-of-Line) 1.6.2 BEOL (Back-End-of-Line) 1.6.3 OSAT (Outsourced Semiconductor Assembly and Test) 1.7 Supply Chains for the TSV Era-Who Makes the TSV 1.7.1 TSVs Fabricated by the Via-First Process 1.7.2 TSVs Fabricated by the Via-Middle Process 1.7.3 TSVs Fabricated by the Via-Last (from the Front Side) Process 1.7.4 TSVs Fabricated by the Via-Last (from the Back Side) Process 1.7.5 How About the Passive TSV Interposers 1.7.6 Who Wants to Fabricate the TSV for Passive Interposers 1.7.7 Summary and Recommendations 1.8 Supply Chains for the TSV Era-Who Does the MEOL, Assembly, and Test 1.8.1 Wide I/O Memory (Face-to-Back) by TSV Via-Middle Fabrication Process 1.8.2 Wide I/O Memory (Face-to-Face) by TSV Via-Middle Fabrication Process 1.8.3 Wide I/O DRAM by TSV Via-Middle Fabrication Process 1.8.4 2.5D IC Integration with TSV/RDL Passive Interposers 1.8.5 Summary and Recommendations 1.9 CMOS Images Sensors with TSVs 1.9.1 Toshiba's DynastronTM 1.9.2 STMicroelectronics' VGA CIS Camera Module 1.9.3 Samsung's S5K4E5YX BSI CIS 1.9.4 Toshiba's HEW4 BSI TCM5103PL 1.9.5 Nemotek's CIS 1.9.6 SONY's ISX014 Stacked Camera Sensor 1.10 MEMS with TSVs 1.10.1 STMicroelectronics’ MEMS Inertial Sensors 1.10.2 Discera's MEME Resonator 1.10.3 Avago's FBAR MEMS Filter 1.11 References 2 Through-Silicon Vias Modeling and Testing 2.1 Introduction 2.2 Electrical Modeling of TSVs 2.2.1 Analytic Model and Equations for a Generic TSV Structure 2.2.2 Verification of the Proposed TSV Model in Frequency Domain 2.2.3 Verification of the Proposed TSV Model in Time Domain 2.2.4 TSV Electrical Design Guideline 2.2.5 Summary and Recommendations
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