VHDL与数字电路设计

图书标准信息

• 作者 王俭、刘传洋、谷慧娟 著
• 出版社 江苏大学出版社
• 出版时间 2009-12
• 版次 1
• ISBN 9787811301212
• 定价 26.00元
• 装帧 平装
• 开本 16开
• 纸张 其他
• 页数 193页
• 正文语种 简体中文

【内容简介】

《VHDL与数字电路设计》系统介绍涉及数字系统设计的多方面原理、技术及应用。主要内容有数字系统的基本设计思想、设计方法和设计步骤，VHDL硬件描述语言，PLD的结构、原理与分类，数字系统设计开发软件平台QuartusⅡ及其使用，常用数字电路的设计方案等；涵盖现代数字系统设计完整过程的三个支撑方面；硬件描述语言、器件、软件开发平台。

【目录】

Chapter1DevelopingDigitalSystem
1.1DigitalSystemsandAnalogSystems
1.2TwoMethodsofDigitalCircuitDesign
1.2.1TraditionalMethod——UsingStandardLogicDevices
1.2.2ModernMethod——UsingProgrammableLogicDevices

1.3IntroductionofProgrammableLogicDevices
1.3.1EarlyProgrammableLogicDevices
1.3.2TodaysProgrammableLogicDevices
1.4Computer-aidedDesignofLogicCircuitsonPLD

1.5DigitalCircuitDesignHierarchy
1.5.1TheSystemandRegisterLevels
1.5.2TheGateLevel
1.5.3TransistorandPhysicalDesignLevels
1.5.4Top-downModularDesign

1.6DesignofPLD
1.6.1TheDesignCycle
1.6.2DigitalCircuitModeling
1.6.3DesignSynthesisandCaptureTools
1.6.4LogicSimulation
1.6.5Librariesand1PCore
PROBLEMS

Chapter2ProgrammableLogicDevices
2.1SemicustomLogicDevices
2.2ProgrammableLogicArrays
2.2.1Two-levelAND-ORArrays
2.2.2PLACircuitStructures
2.2.3RealizingLogicFunctionswithPLAs
2.2.4OutputPolarityOptions

2.3ProgrammableArrayLogic
2.3.1PALCircuitStructures
2.3.2RealizingLogicFunctionswithPALs
2.3.3BidirectionalPinsandFeedbackLines
2.3.4ProgrammableLogicMacrocells
2.4ComplexProgrammableLogicDevices（CPLDs）

2.5Field-ProgrammableGateArrays
2.5.1ProgrammableGateArrays
2.5.2LogicCellArrays
2.5.3Interconnections
PROBLEMS

Chapter3VHDL——AProgrammingLanguage
3.1VHDLDesignEntity
3.1.1EntityDeclaration
3.1.2Architecture
3.2Package
3.3UsingSubcircuits

3.4DataObjects
3.4.1DataObjectNames
3.4.2DataObjectValuesandNumbers

3.5SignalDataObjects
3.5.1BITandBIT_VECTORTypes
3.5.2STD_LOGICandSTD_LOGIC_VECTORTypes
3.5.3SIGNEDandUNSIGNEDTypes
3.5.4INTEGERType
3.5.5BOOLEANType

3.6CONSTANTandVARIABLEDataObjects
3.6.1CONSTANTType
3.6.2VARIABLEType
3.7TypeConversion
3.8Operators

3.9ConcurrentAssignmentStatements
3.9.1SimpleSignalAssignment
3.9.2SelectedSignalAssignment
3.9.3ConditionalSignalAssignment

3.10SequentialAssignmentStatements
3.10.1IFStatement
3.10.2CASEStatement
3.10.3LOOPStatements
3.10.4PROCESSStatement
3.10.5StatementOrdering
3.10.6UsingaVARIABLEinaProcess

3.11ThreeOtherStatements
3.11.1GENERATEStatement
3.11.2DefininganEntitywithGENERICs
3.11.3UsingSubcircuitswithGENERICParameters
PROBLEMS

Chapter4UsingVHDLforDescribingLogicCircuits
4.1DescribingCombinationalCircuits
4.1.1VHDLCodeofMultiplexer
4.1.2VHDLCodeofDecoder
4.1.3VHDLCodeofEncoder
4.1.4VHDLCodeofComparator
4.1.5VHDLCodeofanArithmeticLogicUnit

4.2DesigningSequentialCircuits
4.2.1ImpliedMemory
4.2.2VHDLofLatches
4.2.3VHDLCodeofFlip-Flops
4.2.4VHDLCodeofRegisters
4.2.5VHDLCodeofCounters

4.3State-MachineDesignforVHDL
4.3.1Introduction
4.3.2BasicHDLCoding
4.3.3StateAssignment
4.3.4CodingStateTransitions
PROBLEMS
Chapter5VHDLDesignUsingQuartusⅡ
5.1TypicalCADFlow
5.2GettingStarted
5.3StartingaNewProject
5.4DesignEntryUsingVHDLCode
5.4.1UsingtheQuartusI1TextEditor
5.4.2UsingVHDLTemplates
5.4.3AddingDesignFilestoaProject
5.5CompilingtheDesignedCircuit
5.6PinAssignment

5.7SimulatingtheDesignedCircuit
5.7.1CreatingtheWaveforms
5.7.2PerformingtheSimulation
5.7.3FunctionalSimulation
5.7.4TimingSimulation
5.8ProgrammingandConfiguringtheCPLDDevice
5.9TestingtheDesignedCircuit
PROBLEMS

Chapter6Experiments
6.1DesigningaCountingClock
6.1.1Functions
6.1.2Preparations
6.1.3ModuleSpecificationandPinSignalDefinitions
6.1.4VHDLSourceCodes

6.2DesigningaDigitalFrequencyMeter
6.2.1FunctionsRequirements
6.2.2Preparations
6.2.3VHDLSourceCodes

6.3DesigninganA/DSamplingController
6.3.1FunctionsRequirements
6.3.2Preparations
6.3.3VHDLSourceCodes
Glossary
References
AppendixInternetWebSites