3DIC集成和封装
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四川成都
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作者（美）刘汉诚（John H. Lau）
出版社清华大学出版社
ISBN9787302600657
出版时间2022-04
装帧平装
开本16开
纸张胶版纸
定价129元
货号29420767
上书时间2023-05-16
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【编辑推荐】:
（1）源自工程实践。基于作者40多年的集成电路研发和制造经验，注重封装工艺技术和实际解决方案，是工程应用的实用指南。
（3）聚焦核心技术。重点介绍TSV，应力传感器，微凸点，RDL，硅中介层，芯片/芯片键合，芯片/晶圆键合，MEMS、LED、CMOS图像传感器的3D集成，以及热管理、可靠性等关键技术问题。
（2）拓展国际视野。洞悉国际前沿技术方向和发展趋势，熟悉先进技术和主流产品，有助于快速跟踪、独立发展相关核心技术。
（4）适合作为教材。源自作者开设的相关课程，配套PPT课件，内容系统全面，知识脉络清晰，讲解重点突出，有助于培养专业技术人才。
（5）应用领域广泛。3D集成是集成电路技术发展的重要创新方向，是实现电子产品微型化、高性能、低成本、低功耗的重要手段。
【内容简介】:
本书系统介绍用于电子、光电子和MEMS器件的2.5D、3D以及3D IC集成和封装技术的前沿进展和演变趋势，讨论3D IC集成和封装关键技术的主要工艺问题和解决方案。主要内容包括半导体工业中的集成电路发展，摩尔定律的起源和演变历史，三维集成和封装的优势和挑战，TSV制程与模型、晶圆减薄与薄晶圆在封装组装过程中的拿持晶圆键合技术、三维堆叠的微凸点制作与组装技术、3D硅集成、2.5D/3D IC和无源转接板的3D IC集成、三维器件集成的热管理技术、封装基板技术，以及存储器、LED、MEMS、CIS 3D IC集成等关键技术问题，最后讨论PoP、Fanin WLP、eWLP、ePLP等技术。本书主要读者对象为微电子领域的研究生和从事相关领域的科学研究和工程技术人员。
【作者简介】:
刘汉诚（John H. Lau），伊利诺伊大学香槟分校理论与应用力学博士，不列颠哥伦比亚大学结构工程硕士，威斯康星大学麦迪逊分校工程力学硕士，菲尔莱狄更斯大学管理科学硕士，台湾大学土木工程学士。
历任台湾欣兴电子股份有限公司CTO、香港ASM太平洋科技有限公司高级技术顾问、台湾工业技术研究院研究员、香港科技大学客座教授、新加坡微电子研究院MMC实验室主任、惠普实验室/安捷伦公司资深科学家（超过25年）。
拥有40多年的集成电路研发和制造经验，专业领域包括集成电路的设计、分析、材料、工艺、制造、认证、可靠性、测试和热管理等，目前研究领域为芯片异构集成、SiP、TSV、扇出/扇入晶圆/面板级封装、MEMS、mini/ micro LED、3D IC集成、SMT和焊接力学等。
发表480多篇论文，发明30多项专利，举办 300多场讲座，撰写20多部教科书（涉及3D IC 集成、TSV、先进 MEMS 封装、倒装芯片 WLP、面积阵列封装、高密度 PCB、SMT、DCA、无铅材料、焊接、制造和可靠性等领域）。
ASME Fellow、IEEE life Fellow、IMAPS Fellow，积极参与ASME、IEEE和IMAPS的多项技术活动。获得ASME、IEEE、SME等协会颁发的多项荣誉，包括IEEE/ECTC最佳会议论文（1989)、IEEE/EPTC最佳论文奖(2009)、ASME Transactions最佳论文奖(电子封装杂志，2000)、IEEE Transactions最佳论文奖(CPMT，2010)、ASME/EEP杰出技术成就奖(1998)、IEEE/CPMT电子制造技术奖(1994)、IEEE/CPMT杰出技术成就奖(2000)、IEEE/CPMT杰出持续技术贡献奖（2010）、SME电子制造全面卓越奖（2001）、潘文渊杰出研究奖（2011）、IEEE 继续教育杰出成就奖（2000）、IEEE CPMT技术领域奖（2013）和 ASME 伍斯特·里德·华纳奖章（2015）等。
【目录】:
1 3D Integration for Semiconductor IC Packaging
1.1 Introduction
1.2 3D Integration
1.3 3D IC Packaging
1.4 3D Si Integration
1.5 3D IC Integration
1.5.1 Hybrid Memory Cube
1.5.2 Wide I/O DRAM and Wide I/O 2
1.5.3 High Bandwidth Memory
1.5.4 Wide I/O Memory (or Logic-on-Logic)
1.5.5 Passive Interposer (2.5D IC Integration)
1.6 Supply Chains before the TSV Era
1.6.1 FEOL (Front-End-of-Line)
1.6.2 BEOL (Back-End-of-Line)
1.6.3 OSAT (Outsourced Semiconductor Assembly and Test)
1.7 Supply Chains for the TSV Era—Who Makes the TSV?
1.7.1 TSVs Fabricated by the Via-First Process
1.7.2 TSVs Fabricated by the Via-Middle Process
1.7.3 TSVs Fabricated by the Via-Last (from the Front Side) Process
1.7.4 TSVs Fabricated by the Via-Last (from the Back Side) Process
1.7.5 How About the Passive TSV Interposers?
1.7.6 Who Wants to Fabricate the TSV for Passive Interposers?
1.7.7 Summary and Recommendations
1.8 Supply Chains for the TSV Era—Who Does the MEOL,Assembly, and Test?
1.8.1 Wide I/O Memory (Face-to-Back) by TSV Via-Middle Fabrication Process
1.8.2 Wide I/O Memory (Face-to-Face) by TSV Via-Middle Fabrication Process
1.8.3 Wide I/O DRAM by TSV Via-Middle Fabrication Process
1.8.4 2.5D IC Integration with TSV/RDL Passive Interposers
1.8.5 Summary and Recommendations
1.9 CMOS Images Sensors with TSVs
1.9.1 Toshiba’s Dynastron TM
1.9.2 STMicroelectronics’ VGA CIS Camera Module
1.9.3 Samsung’s S5K4E5YX BSI CIS
1.9.4 Toshiba’s HEW4 BSI TCM5103PL
1.9.5 Nemotek’s CIS
1.9.6 SONY’s ISX014 Stacked Camera Sensor
1.10 MEMS with TSVs
1.10.1 STMicroelectronics’ MEMS Inertial Sensors
1.10.2 Discera’s MEME Resonator
1.10.3 Avago’s FBAR MEMS Filter
1.11 References
2 Through-Silicon Vias Modeling and Testing
2.1 Introduction
2.2 Electrical Modeling of TSVs
2.2.1 Analytic Model and Equations for a Generic TSV Structure
2.2.2 Verification of the Proposed TSV Model in Frequency Domain
2.2.3 Verification of the Proposed TSV Model in Time Domain
2.2.4 TSV Electrical Design Guideline
2.2.5 Summary and Recommendations
2.3 Thermal Modeling of TSVs
2.3.1 Cu-Filled TSV Equivalent Thermal Conductivity Extraction
2.3.2 Thermal Behavior of a TSV Cell
2.3.3 Cu-Filled TSV Equivalent Thermal Conductivity Equations
2.3.4 Verification of the TSV Equivalent Thermal Conductivity Equations
2.3.5 Summary and Recommendations
2.4 Mechanical Modeling and Testing of TSVs
2.4.1 TEM between the Cu-Filled TSV and Its Surrounding Si
2.4.2 Experimental Results on Cu Pumping during Manufacturing
2.4.3 Cu Pumping under Thermal Shock Cycling
2.4.4 Keep-Out-Zone of Cu-Filled TSVs
2.4.5 Summary and Recommendations
2.5 References
3 Stress Sensors for Thin-Wafer Handling and Strength Measurement
3.1 Introduction
3.2 Design and Fabrication of Piezoresistive Stress Sensors
3.2.1 Design of Piezoresistive Stress Sensors
3.2.2 Fabrication of the Stress Sensors
3.2.3 Summary and Recommendations
3.3 Application of Stress Sensors in Thin-Wafer Handling
3.3.1 Design, Fabrication, and Calibration of Piezoresistive Stress Sensors
3.3.2 Stress Measurement in Wafer after Thinning
3.3.3 Summary and Recommendations
3.4 Application of Stress Sensors in Wafer Bumping
3.4.1 Stresses after UBM Fabrication
3.4.2 Stresses after Dry-Film Process
3.4.3 Stresses after Solder Bumping Process
3.4.4 Summary and Recommendations
3.5 Application of Stress Sensors in Drop Test of Embedded Ultrathin Chips
3.5.1 Test Vehicle and Fabrication
3.5.2 Experimental Setup and Procedure
3.5.3 In-Situ Stress Measurement Results
3.5.4 Reliability Testing
3.5.5 Summary and Recommendations
3.6 References
4 Package Substrate Technologies
4.1 Introduction
4.2 Package Substrate with Build-up Layers for Flip Chip 3D IC Integration
4.2.1 Surface Laminate Circuit Technology
4.2.2 The Trend in Package Substrate with Build-up Layers
4.2.3 Summary and Recommendations
4.3 Coreless Package Substrates
4.3.1 Advantages and Disadvantages of Coreless Package Substrates
4.3.2 Substitution of Si Interposer by Coreless Substrates
4.3.3 Warpage Problem and Solution of Coreless Substrates
4.3.4 Summary and Recommendations
4.4 Recent Advance of Package Substrate with Build-up Layer
4.4.1 Thin-Film Layers on Top of Build-up Layer of Package Substrate
4.4.2 Warpage and Qualification Results
4.4.3 Summary and Recommendations 4.5 References
5 Microbumps: Fabrication, Assembly, and Reliability
5.1 Introduction
5.2 Fabrication, Assembly, and Reliability of 25-μm-Pitch Microbumps
5.2.1 Test Vehicle
5.2.2 Structure of the Microbumps
5.2.3 Structure of the ENIG Pads
5.2.4 Fabrication of the 25-μm-Pitch Microbumps
5.2.5 Fabrication of ENIG Bonding Pads on Si Carrier
5.2.6 Thermal Compression Bonding Assembly
5.2.7 Evaluation of the Underfill
5.2.8 Reliability Assessment
5.2.9 Summary and Recommendations
5.3 Fabrication, Assembly, and Reliability of 20-μm-Pitch Microbumps
5.3.1 Test Vehicle
5.3.2 Assembly of Test Vehicle
5.3.3 Formation of Microjoints by Thermocompression Bonding
5.3.4 Microgap Filling
5.3.5 Reliability Test
5.3.6 Reliability Test Results and Discussion
5.3.7 Failure Mechanism of the Microjoints
5.3.8 Summary and Recommendations
5.4 Fabrication, Assembly, and Reliability of 15-μm-Pitch Microbumps
5.4.1 Microbumps and UBM Pads of the Test Vehicle
5.4.2 Assembly
5.4.3 Assembly with CuSn Solder Microbump and ENIG Pad
5.4.4 Assembly with CuSn Solder Microbump and CuSn Solder Microbump
5.4.5 Evaluation of Underfill
5.4.6 Summary and Recommendations
5.5 References
6 3D Si Integration
6.1 Introduction
6.2 The Electronic Industry
6.3 Moore’s Law and More-Than-Moore
6.4 The Origin of 3D Integration
6.5 Overview and Outlook of 3D Si Integration
6.5.1 Bonding Methods for 3D Si Integration
6.5.2 Cu-to-Cu (W2W) Bonding
6.5.3 Cu-to-Cu (W2W) Bonding with Post-Annealing
6.5.4 Cu-to-Cu (W2W) Bonding at Room Temperature
6.5.5 SiO 2 -to-SiO 2 (W2W) Bonding
6.5.6 A Few Notes on W2W Bonding
6.6 3D Si Integration Technology Challenges
6.7 3D Si Integration EDA Challenges
6.8 Summary and Recommendations
6.9 References
7 2.5D/3D IC Integration
7.1 Introduction
7.2 TSV Process for 3D IC Integration
7.2.1 Tiny Vias on a Chip
7.2.2 Via-First Process
7.2.3 Via-Middle Process
7.2.4 Via-Last from the Front-Side Process
7.2.5 Via-Last from the Back-Side Process
7.2.6 Summary and Recommendations
7.3 The Potential Application of 3D IC Integration
7.4 Memory-Chip Stacking
7.4.1 The Chips
7.4.2 The Potential Products
7.4.3 Assembly Process
7.5 Wide I/O Memory or Logic-on-Logic
7.5.1 The Chips
7.5.2 The Potential Products
7.5.3 Assembly Process
7.6 Wide I/O DRAM or Hybrid Memory Cube
7.6.1 The Chips
7.6.2 The Potential Products
7.6.3 Assembly Process
7.7 Wide I/O 2 and High Bandwidth Memory
7.8 Wide I/O Interface (2.5D IC Integration)
7.8.1 Real Applications of TSV/RDL Passive Interposers
7.8.2 Fabrication of Interposers
7.8.3 Fabrication of TSVs
7.8.4 Fabrication of RDLs
7.8.5 Fabrication of RDLs—Polymer/Cu-Plating Method
7.8.6 Fabrication of RDLs—Cu Damascene Method
7.8.7 A Note on Contact Aligner for Cu Damascene Method
7.8.8 Back-Side Processing and Assembly
7.8.9 Summary and Recommendations
7.9 Thin-Wafer Handling
7.9.1 Conventional Thin-Wafer Handling Method
7.9.2 TI’s TSV-WCSP Integration Process
7.9.3 TSMC’s Thin-Wafer Handling with Polymer
7.9.4 TSMC’s Thin-Wafer Handling without Temporary Bonding and De-Bonding
7.9.5 Thin-Wafer Handling with a Heat-Spreader Wafer
7.9.6 Summary and Recommendations
7.10 References
8 3D IC Integration with Passive Interposer
8.1 Introduction
8.2 3D IC Integration with TSV/RDL Interposer
8.3 TSV/RDL Interposer with Double-Sided Chip Attachments
8.3.1 Th
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